1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smstateen 132 description: | 133 The standard Smstateen extension for controlling access to CSRs 134 added by other RISC-V extensions in H/S/VS/U/VU modes and as 135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 136 137 - const: ssaia 138 description: | 139 The standard Ssaia supervisor-level extension for the advanced 140 interrupt architecture for supervisor-mode-visible csr and 141 behavioural changes to interrupts as frozen at commit ccbddab 142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 143 144 - const: sscofpmf 145 description: | 146 The standard Sscofpmf supervisor-level extension for count overflow 147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 148 to manually trigger workflow. (#2)") of riscv-count-overflow. 149 150 - const: sstc 151 description: | 152 The standard Sstc supervisor-level extension for time compare as 153 ratified at commit 3f9ed34 ("Add ability to manually trigger 154 workflow. (#2)") of riscv-time-compare. 155 156 - const: svinval 157 description: 158 The standard Svinval supervisor-level extension for fine-grained 159 address-translation cache invalidation as ratified in the 20191213 160 version of the privileged ISA specification. 161 162 - const: svnapot 163 description: 164 The standard Svnapot supervisor-level extensions for napot 165 translation contiguity as ratified in the 20191213 version of the 166 privileged ISA specification. 167 168 - const: svpbmt 169 description: 170 The standard Svpbmt supervisor-level extensions for page-based 171 memory types as ratified in the 20191213 version of the privileged 172 ISA specification. 173 174 - const: zacas 175 description: | 176 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 177 is supported as ratified at commit 5059e0ca641c ("update to 178 ratified") of the riscv-zacas. 179 180 - const: zawrs 181 description: | 182 The Zawrs extension for entering a low-power state or for trapping 183 to a hypervisor while waiting on a store to a memory location, as 184 ratified in commit 98918c844281 ("Merge pull request #1217 from 185 riscv/zawrs") of riscv-isa-manual. 186 187 - const: zba 188 description: | 189 The standard Zba bit-manipulation extension for address generation 190 acceleration instructions as ratified at commit 6d33919 ("Merge pull 191 request #158 from hirooih/clmul-fix-loop-end-condition") of 192 riscv-bitmanip. 193 194 - const: zbb 195 description: | 196 The standard Zbb bit-manipulation extension for basic bit-manipulation 197 as ratified at commit 6d33919 ("Merge pull request #158 from 198 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 199 200 - const: zbc 201 description: | 202 The standard Zbc bit-manipulation extension for carry-less 203 multiplication as ratified at commit 6d33919 ("Merge pull request 204 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 205 206 - const: zbkb 207 description: 208 The standard Zbkb bitmanip instructions for cryptography as ratified 209 in version 1.0 of RISC-V Cryptography Extensions Volume I 210 specification. 211 212 - const: zbkc 213 description: 214 The standard Zbkc carry-less multiply instructions as ratified 215 in version 1.0 of RISC-V Cryptography Extensions Volume I 216 specification. 217 218 - const: zbkx 219 description: 220 The standard Zbkx crossbar permutation instructions as ratified 221 in version 1.0 of RISC-V Cryptography Extensions Volume I 222 specification. 223 224 - const: zbs 225 description: | 226 The standard Zbs bit-manipulation extension for single-bit 227 instructions as ratified at commit 6d33919 ("Merge pull request #158 228 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 229 230 - const: zca 231 description: | 232 The Zca extension part of Zc* standard extensions for code size 233 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 234 RV64 as it contains no instructions") of riscv-code-size-reduction, 235 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 236 of zc.adoc to src tree."). 237 238 - const: zcb 239 description: | 240 The Zcb extension part of Zc* standard extensions for code size 241 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 242 RV64 as it contains no instructions") of riscv-code-size-reduction, 243 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 244 of zc.adoc to src tree."). 245 246 - const: zcd 247 description: | 248 The Zcd extension part of Zc* standard extensions for code size 249 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 250 RV64 as it contains no instructions") of riscv-code-size-reduction, 251 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 252 of zc.adoc to src tree."). 253 254 - const: zcf 255 description: | 256 The Zcf extension part of Zc* standard extensions for code size 257 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 258 RV64 as it contains no instructions") of riscv-code-size-reduction, 259 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 260 of zc.adoc to src tree."). 261 262 - const: zcmop 263 description: 264 The standard Zcmop extension version 1.0, as ratified in commit 265 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 266 267 - const: zfa 268 description: 269 The standard Zfa extension for additional floating point 270 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 271 riscv-isa-manual. 272 273 - const: zfh 274 description: 275 The standard Zfh extension for 16-bit half-precision binary 276 floating-point instructions, as ratified in commit 64074bc ("Update 277 version numbers for Zfh/Zfinx") of riscv-isa-manual. 278 279 - const: zfhmin 280 description: 281 The standard Zfhmin extension which provides minimal support for 282 16-bit half-precision binary floating-point instructions, as ratified 283 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 284 riscv-isa-manual. 285 286 - const: zk 287 description: 288 The standard Zk Standard Scalar cryptography extension as ratified 289 in version 1.0 of RISC-V Cryptography Extensions Volume I 290 specification. 291 292 - const: zkn 293 description: 294 The standard Zkn NIST algorithm suite extensions as ratified in 295 version 1.0 of RISC-V Cryptography Extensions Volume I 296 specification. 297 298 - const: zknd 299 description: | 300 The standard Zknd for NIST suite: AES decryption instructions as 301 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 302 specification. 303 304 - const: zkne 305 description: | 306 The standard Zkne for NIST suite: AES encryption instructions as 307 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 308 specification. 309 310 - const: zknh 311 description: | 312 The standard Zknh for NIST suite: hash function instructions as 313 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 314 specification. 315 316 - const: zkr 317 description: 318 The standard Zkr entropy source extension as ratified in version 319 1.0 of RISC-V Cryptography Extensions Volume I specification. 320 This string being present means that the CSR associated to this 321 extension is accessible at the privilege level to which that 322 device-tree has been provided. 323 324 - const: zks 325 description: 326 The standard Zks ShangMi algorithm suite extensions as ratified in 327 version 1.0 of RISC-V Cryptography Extensions Volume I 328 specification. 329 330 - const: zksed 331 description: | 332 The standard Zksed for ShangMi suite: SM4 block cipher instructions 333 as ratified in version 1.0 of RISC-V Cryptography Extensions 334 Volume I specification. 335 336 - const: zksh 337 description: | 338 The standard Zksh for ShangMi suite: SM3 hash function instructions 339 as ratified in version 1.0 of RISC-V Cryptography Extensions 340 Volume I specification. 341 342 - const: zkt 343 description: 344 The standard Zkt for data independent execution latency as ratified 345 in version 1.0 of RISC-V Cryptography Extensions Volume I 346 specification. 347 348 - const: zicbom 349 description: 350 The standard Zicbom extension for base cache management operations as 351 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 352 353 - const: zicbop 354 description: 355 The standard Zicbop extension for cache-block prefetch instructions 356 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 357 riscv-CMOs. 358 359 - const: zicboz 360 description: 361 The standard Zicboz extension for cache-block zeroing as ratified 362 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 363 364 - const: zicntr 365 description: 366 The standard Zicntr extension for base counters and timers, as 367 ratified in the 20191213 version of the unprivileged ISA 368 specification. 369 370 - const: zicond 371 description: 372 The standard Zicond extension for conditional arithmetic and 373 conditional-select/move operations as ratified in commit 95cf1f9 374 ("Add changes requested by Ved during signoff") of riscv-zicond. 375 376 - const: zicsr 377 description: | 378 The standard Zicsr extension for control and status register 379 instructions, as ratified in the 20191213 version of the 380 unprivileged ISA specification. 381 382 This does not include Chapter 10, "Counters", which documents 383 special case read-only CSRs, that were moved into the Zicntr and 384 Zihpm extensions after the ratification of the 20191213 version of 385 the unprivileged specification. 386 387 - const: zifencei 388 description: 389 The standard Zifencei extension for instruction-fetch fence, as 390 ratified in the 20191213 version of the unprivileged ISA 391 specification. 392 393 - const: zihintpause 394 description: 395 The standard Zihintpause extension for pause hints, as ratified in 396 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 397 398 - const: zihintntl 399 description: 400 The standard Zihintntl extension for non-temporal locality hints, as 401 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 402 riscv-isa-manual. 403 404 - const: zihpm 405 description: 406 The standard Zihpm extension for hardware performance counters, as 407 ratified in the 20191213 version of the unprivileged ISA 408 specification. 409 410 - const: zimop 411 description: 412 The standard Zimop extension version 1.0, as ratified in commit 413 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 414 415 - const: ztso 416 description: 417 The standard Ztso extension for total store ordering, as ratified 418 in commit 2e5236 ("Ztso is now ratified.") of the 419 riscv-isa-manual. 420 421 - const: zvbb 422 description: 423 The standard Zvbb extension for vectored basic bit-manipulation 424 instructions, as ratified in commit 56ed795 ("Update 425 riscv-crypto-spec-vector.adoc") of riscv-crypto. 426 427 - const: zvbc 428 description: 429 The standard Zvbc extension for vectored carryless multiplication 430 instructions, as ratified in commit 56ed795 ("Update 431 riscv-crypto-spec-vector.adoc") of riscv-crypto. 432 433 - const: zve32f 434 description: 435 The standard Zve32f extension for embedded processors, as ratified 436 in commit 6f702a2 ("Vector extensions are now ratified") of 437 riscv-v-spec. 438 439 - const: zve32x 440 description: 441 The standard Zve32x extension for embedded processors, as ratified 442 in commit 6f702a2 ("Vector extensions are now ratified") of 443 riscv-v-spec. 444 445 - const: zve64d 446 description: 447 The standard Zve64d extension for embedded processors, as ratified 448 in commit 6f702a2 ("Vector extensions are now ratified") of 449 riscv-v-spec. 450 451 - const: zve64f 452 description: 453 The standard Zve64f extension for embedded processors, as ratified 454 in commit 6f702a2 ("Vector extensions are now ratified") of 455 riscv-v-spec. 456 457 - const: zve64x 458 description: 459 The standard Zve64x extension for embedded processors, as ratified 460 in commit 6f702a2 ("Vector extensions are now ratified") of 461 riscv-v-spec. 462 463 - const: zvfh 464 description: 465 The standard Zvfh extension for vectored half-precision 466 floating-point instructions, as ratified in commit e2ccd05 467 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 468 469 - const: zvfhmin 470 description: 471 The standard Zvfhmin extension for vectored minimal half-precision 472 floating-point instructions, as ratified in commit e2ccd05 473 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 474 475 - const: zvkb 476 description: 477 The standard Zvkb extension for vector cryptography bit-manipulation 478 instructions, as ratified in commit 56ed795 ("Update 479 riscv-crypto-spec-vector.adoc") of riscv-crypto. 480 481 - const: zvkg 482 description: 483 The standard Zvkg extension for vector GCM/GMAC instructions, as 484 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 485 of riscv-crypto. 486 487 - const: zvkn 488 description: 489 The standard Zvkn extension for NIST algorithm suite instructions, as 490 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 491 of riscv-crypto. 492 493 - const: zvknc 494 description: 495 The standard Zvknc extension for NIST algorithm suite with carryless 496 multiply instructions, as ratified in commit 56ed795 ("Update 497 riscv-crypto-spec-vector.adoc") of riscv-crypto. 498 499 - const: zvkned 500 description: 501 The standard Zvkned extension for Vector AES block cipher 502 instructions, as ratified in commit 56ed795 ("Update 503 riscv-crypto-spec-vector.adoc") of riscv-crypto. 504 505 - const: zvkng 506 description: 507 The standard Zvkng extension for NIST algorithm suite with GCM 508 instructions, as ratified in commit 56ed795 ("Update 509 riscv-crypto-spec-vector.adoc") of riscv-crypto. 510 511 - const: zvknha 512 description: | 513 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 514 hash (SHA-256 only) instructions, as ratified in commit 515 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 516 517 - const: zvknhb 518 description: | 519 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 520 hash (SHA-256 and SHA-512) instructions, as ratified in commit 521 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 522 523 - const: zvks 524 description: 525 The standard Zvks extension for ShangMi algorithm suite 526 instructions, as ratified in commit 56ed795 ("Update 527 riscv-crypto-spec-vector.adoc") of riscv-crypto. 528 529 - const: zvksc 530 description: 531 The standard Zvksc extension for ShangMi algorithm suite with 532 carryless multiplication instructions, as ratified in commit 56ed795 533 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 534 535 - const: zvksed 536 description: | 537 The standard Zvksed extension for ShangMi suite: SM4 block cipher 538 instructions, as ratified in commit 56ed795 ("Update 539 riscv-crypto-spec-vector.adoc") of riscv-crypto. 540 541 - const: zvksh 542 description: | 543 The standard Zvksh extension for ShangMi suite: SM3 secure hash 544 instructions, as ratified in commit 56ed795 ("Update 545 riscv-crypto-spec-vector.adoc") of riscv-crypto. 546 547 - const: zvksg 548 description: 549 The standard Zvksg extension for ShangMi algorithm suite with GCM 550 instructions, as ratified in commit 56ed795 ("Update 551 riscv-crypto-spec-vector.adoc") of riscv-crypto. 552 553 - const: zvkt 554 description: 555 The standard Zvkt extension for vector data-independent execution 556 latency, as ratified in commit 56ed795 ("Update 557 riscv-crypto-spec-vector.adoc") of riscv-crypto. 558 559 - const: xandespmu 560 description: 561 The Andes Technology performance monitor extension for counter overflow 562 and privilege mode filtering. For more details, see Counter Related 563 Registers in the AX45MP datasheet. 564 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 565 566 allOf: 567 # Zcb depends on Zca 568 - if: 569 contains: 570 const: zcb 571 then: 572 contains: 573 const: zca 574 # Zcd depends on Zca and D 575 - if: 576 contains: 577 const: zcd 578 then: 579 allOf: 580 - contains: 581 const: zca 582 - contains: 583 const: d 584 # Zcf depends on Zca and F 585 - if: 586 contains: 587 const: zcf 588 then: 589 allOf: 590 - contains: 591 const: zca 592 - contains: 593 const: f 594 # Zcmop depends on Zca 595 - if: 596 contains: 597 const: zcmop 598 then: 599 contains: 600 const: zca 601 602allOf: 603 # Zcf extension does not exist on rv64 604 - if: 605 properties: 606 riscv,isa-extensions: 607 contains: 608 const: zcf 609 riscv,isa-base: 610 contains: 611 const: rv64i 612 then: 613 properties: 614 riscv,isa-extensions: 615 not: 616 contains: 617 const: zcf 618 619additionalProperties: true 620... 621