1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27properties: 28 riscv,isa: 29 description: 30 Identifies the specific RISC-V instruction set architecture 31 supported by the hart. These are documented in the RISC-V 32 User-Level ISA document, available from 33 https://riscv.org/specifications/ 34 35 Due to revisions of the ISA specification, some deviations 36 have arisen over time. 37 Notably, riscv,isa was defined prior to the creation of the 38 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 39 implies "zicntr_zicsr_zifencei_zihpm". 40 41 While the isa strings in ISA specification are case 42 insensitive, letters in the riscv,isa string must be all 43 lowercase. 44 $ref: /schemas/types.yaml#/definitions/string 45 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 46 deprecated: true 47 48 riscv,isa-base: 49 description: 50 The base ISA implemented by this hart, as described by the 20191213 51 version of the unprivileged ISA specification. 52 enum: 53 - rv32i 54 - rv64i 55 56 riscv,isa-extensions: 57 $ref: /schemas/types.yaml#/definitions/string-array 58 minItems: 1 59 description: Extensions supported by the hart. 60 items: 61 anyOf: 62 # single letter extensions, in canonical order 63 - const: i 64 description: | 65 The base integer instruction set, as ratified in the 20191213 66 version of the unprivileged ISA specification. 67 68 This does not include Chapter 10, "Counters", which was moved into 69 the Zicntr and Zihpm extensions after the ratification of the 70 20191213 version of the unprivileged specification. 71 72 - const: m 73 description: 74 The standard M extension for integer multiplication and division, as 75 ratified in the 20191213 version of the unprivileged ISA 76 specification. 77 78 - const: a 79 description: 80 The standard A extension for atomic instructions, as ratified in the 81 20191213 version of the unprivileged ISA specification. 82 83 - const: f 84 description: 85 The standard F extension for single-precision floating point, as 86 ratified in the 20191213 version of the unprivileged ISA 87 specification. 88 89 - const: d 90 description: 91 The standard D extension for double-precision floating-point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: q 96 description: 97 The standard Q extension for quad-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: c 102 description: 103 The standard C extension for compressed instructions, as ratified in 104 the 20191213 version of the unprivileged ISA specification. 105 106 - const: b 107 description: 108 The standard B extension for bit manipulation instructions, as 109 ratified in the 20240411 version of the unprivileged ISA 110 specification. The B standard extension comprises instructions 111 provided by the Zba, Zbb, and Zbs extensions. 112 113 - const: v 114 description: 115 The standard V extension for vector operations, as ratified 116 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 117 encoding") of the riscv-v-spec. 118 119 - const: h 120 description: 121 The standard H extension for hypervisors as ratified in the RISC-V 122 Instruction Set Manual, Volume II Privileged Architecture, 123 Document Version 20211203. 124 125 # multi-letter extensions, sorted alphanumerically 126 - const: sha 127 description: | 128 The standard Sha extension for augmented hypervisor extension as 129 ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 130 ("rva23/rvb23 ratified"). 131 132 Sha captures the full set of features that are mandated to be 133 supported along with the H extension. Sha comprises the following 134 extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, 135 Shvstvecd, and Ssstateen. 136 137 - const: shcounterenw 138 description: | 139 The standard Shcounterenw extension for support writable enables 140 in hcounteren for any supported counter, as ratified in RISC-V 141 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 142 ratified state.") 143 144 - const: shgatpa 145 description: | 146 The standard Shgatpa extension indicates that for each supported 147 virtual memory scheme SvNN supported in satp, the corresponding 148 hgatp SvNNx4 mode must be supported. The hgatp mode Bare must 149 also be supported. It is ratified in RISC-V Profiles Version 1.0, 150 with commit b1d806605f87 ("Updated to ratified state.") 151 152 - const: shtvala 153 description: | 154 The standard Shtvala extension for htval be written with the 155 faulting guest physical address in all circumstances permitted by 156 the ISA. It is ratified in RISC-V Profiles Version 1.0, with 157 commit b1d806605f87 ("Updated to ratified state.") 158 159 - const: shvsatpa 160 description: | 161 The standard Shvsatpa extension for vsatp supporting all translation 162 modes supported in satp, as ratified in RISC-V Profiles Version 1.0, 163 with commit b1d806605f87 ("Updated to ratified state.") 164 165 - const: shvstvala 166 description: | 167 The standard Shvstvala extension for vstval provides all needed 168 values as ratified in RISC-V Profiles Version 1.0, with commit 169 b1d806605f87 ("Updated to ratified state.") 170 171 - const: shvstvecd 172 description: | 173 The standard Shvstvecd extension for vstvec supporting Direct mode, 174 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 175 ("Updated to ratified state.") 176 177 - const: smaia 178 description: | 179 The standard Smaia supervisor-level extension for the advanced 180 interrupt architecture for machine-mode-visible csr and behavioural 181 changes to interrupts as frozen at commit ccbddab ("Merge pull 182 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 183 184 - const: smmpm 185 description: | 186 The standard Smmpm extension for M-mode pointer masking as 187 ratified at commit d70011dde6c2 ("Update to ratified state") 188 of riscv-j-extension. 189 190 - const: smnpm 191 description: | 192 The standard Smnpm extension for next-mode pointer masking as 193 ratified at commit d70011dde6c2 ("Update to ratified state") 194 of riscv-j-extension. 195 196 - const: smstateen 197 description: | 198 The standard Smstateen extension for controlling access to CSRs 199 added by other RISC-V extensions in H/S/VS/U/VU modes and as 200 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 201 202 - const: ssaia 203 description: | 204 The standard Ssaia supervisor-level extension for the advanced 205 interrupt architecture for supervisor-mode-visible csr and 206 behavioural changes to interrupts as frozen at commit ccbddab 207 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 208 209 - const: ssccptr 210 description: | 211 The standard Ssccptr extension for main memory (cacheability and 212 coherence) hardware page-table reads, as ratified in RISC-V 213 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 214 ratified state.") 215 216 - const: sscofpmf 217 description: | 218 The standard Sscofpmf supervisor-level extension for count overflow 219 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 220 to manually trigger workflow. (#2)") of riscv-count-overflow. 221 222 - const: sscounterenw 223 description: | 224 The standard Sscounterenw extension for support writable enables 225 in scounteren for any supported counter, as ratified in RISC-V 226 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 227 ratified state.") 228 229 - const: ssnpm 230 description: | 231 The standard Ssnpm extension for next-mode pointer masking as 232 ratified at commit d70011dde6c2 ("Update to ratified state") 233 of riscv-j-extension. 234 235 - const: ssstateen 236 description: | 237 The standard Ssstateen extension for supervisor-mode view of the 238 state-enable extension, as ratified in RISC-V Profiles Version 1.0, 239 with commit b1d806605f87 ("Updated to ratified state.") 240 241 - const: sstc 242 description: | 243 The standard Sstc supervisor-level extension for time compare as 244 ratified at commit 3f9ed34 ("Add ability to manually trigger 245 workflow. (#2)") of riscv-time-compare. 246 247 - const: sstvala 248 description: | 249 The standard Sstvala extension for stval provides all needed values 250 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 251 ("Updated to ratified state.") 252 253 - const: sstvecd 254 description: | 255 The standard Sstvecd extension for stvec supports Direct mode as 256 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 257 ("Updated to ratified state.") 258 259 - const: ssu64xl 260 description: | 261 The standard Ssu64xl extension for UXLEN=64 must be supported, as 262 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 263 ("Updated to ratified state.") 264 265 - const: svade 266 description: | 267 The standard Svade supervisor-level extension for SW-managed PTE A/D 268 bit updates as ratified in the 20240213 version of the privileged 269 ISA specification. 270 271 Both Svade and Svadu extensions control the hardware behavior when 272 the PTE A/D bits need to be set. The default behavior for the four 273 possible combinations of these extensions in the device tree are: 274 1) Neither Svade nor Svadu present in DT => It is technically 275 unknown whether the platform uses Svade or Svadu. Supervisor 276 software should be prepared to handle either hardware updating 277 of the PTE A/D bits or page faults when they need updated. 278 2) Only Svade present in DT => Supervisor must assume Svade to be 279 always enabled. 280 3) Only Svadu present in DT => Supervisor must assume Svadu to be 281 always enabled. 282 4) Both Svade and Svadu present in DT => Supervisor must assume 283 Svadu turned-off at boot time. To use Svadu, supervisor must 284 explicitly enable it using the SBI FWFT extension. 285 286 - const: svadu 287 description: | 288 The standard Svadu supervisor-level extension for hardware updating 289 of PTE A/D bits as ratified in the 20240528 version of the 290 privileged ISA specification. Please refer to Svade dt-binding 291 description for more details. 292 293 - const: svinval 294 description: 295 The standard Svinval supervisor-level extension for fine-grained 296 address-translation cache invalidation as ratified in the RISC-V 297 Instruction Set Manual, Volume II Privileged Architecture, 298 Document Version 20211203. 299 300 - const: svnapot 301 description: 302 The standard Svnapot supervisor-level extensions for napot 303 translation contiguity as ratified in the RISC-V Instruction Set 304 Manual, Volume II Privileged Architecture, Document Version 305 20211203. 306 307 - const: svpbmt 308 description: 309 The standard Svpbmt supervisor-level extensions for page-based 310 memory types as ratified in the RISC-V Instruction Set Manual, 311 Volume II Privileged Architecture, Document Version 20211203. 312 313 - const: svrsw60t59b 314 description: 315 The Svrsw60t59b extension for providing two more bits[60:59] to 316 PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved 317 for SW bits 60:59") of riscv-non-isa/riscv-iommu. 318 319 - const: svvptc 320 description: 321 The standard Svvptc supervisor-level extension for 322 address-translation cache behaviour with respect to invalid entries 323 as ratified at commit 4a69197e5617 ("Update to ratified state") of 324 riscv-svvptc. 325 326 - const: za64rs 327 description: 328 The standard Za64rs extension for reservation set size of at most 329 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit 330 b1d806605f87 ("Updated to ratified state.") 331 332 - const: zaamo 333 description: | 334 The standard Zaamo extension for atomic memory operations as 335 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 336 (#1304)") of the unprivileged ISA specification. 337 338 - const: zabha 339 description: | 340 The Zabha extension for Byte and Halfword Atomic Memory Operations 341 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 342 riscv-zabha. 343 344 - const: zacas 345 description: | 346 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 347 is supported as ratified at commit 5059e0ca641c ("update to 348 ratified") of the riscv-zacas. 349 350 - const: zalasr 351 description: | 352 The standard Zalasr extension for load-acquire/store-release as frozen 353 at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. 354 355 - const: zalrsc 356 description: | 357 The standard Zalrsc extension for load-reserved/store-conditional as 358 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 359 (#1304)") of the unprivileged ISA specification. 360 361 - const: zawrs 362 description: | 363 The Zawrs extension for entering a low-power state or for trapping 364 to a hypervisor while waiting on a store to a memory location, as 365 ratified in commit 98918c844281 ("Merge pull request #1217 from 366 riscv/zawrs") of riscv-isa-manual. 367 368 - const: zba 369 description: | 370 The standard Zba bit-manipulation extension for address generation 371 acceleration instructions as ratified at commit 6d33919 ("Merge pull 372 request #158 from hirooih/clmul-fix-loop-end-condition") of 373 riscv-bitmanip. 374 375 - const: zbb 376 description: | 377 The standard Zbb bit-manipulation extension for basic bit-manipulation 378 as ratified at commit 6d33919 ("Merge pull request #158 from 379 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 380 381 - const: zbc 382 description: | 383 The standard Zbc bit-manipulation extension for carry-less 384 multiplication as ratified at commit 6d33919 ("Merge pull request 385 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 386 387 - const: zbkb 388 description: 389 The standard Zbkb bitmanip instructions for cryptography as ratified 390 in version 1.0 of RISC-V Cryptography Extensions Volume I 391 specification. 392 393 - const: zbkc 394 description: 395 The standard Zbkc carry-less multiply instructions as ratified 396 in version 1.0 of RISC-V Cryptography Extensions Volume I 397 specification. 398 399 - const: zbkx 400 description: 401 The standard Zbkx crossbar permutation instructions as ratified 402 in version 1.0 of RISC-V Cryptography Extensions Volume I 403 specification. 404 405 - const: zbs 406 description: | 407 The standard Zbs bit-manipulation extension for single-bit 408 instructions as ratified at commit 6d33919 ("Merge pull request #158 409 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 410 411 - const: zca 412 description: | 413 The Zca extension part of Zc* standard extensions for code size 414 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 415 RV64 as it contains no instructions") of riscv-code-size-reduction, 416 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 417 of zc.adoc to src tree."). 418 419 - const: zcb 420 description: | 421 The Zcb extension part of Zc* standard extensions for code size 422 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 423 RV64 as it contains no instructions") of riscv-code-size-reduction, 424 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 425 of zc.adoc to src tree."). 426 427 - const: zcd 428 description: | 429 The Zcd extension part of Zc* standard extensions for code size 430 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 431 RV64 as it contains no instructions") of riscv-code-size-reduction, 432 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 433 of zc.adoc to src tree."). 434 435 - const: zcf 436 description: | 437 The Zcf extension part of Zc* standard extensions for code size 438 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 439 RV64 as it contains no instructions") of riscv-code-size-reduction, 440 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 441 of zc.adoc to src tree."). 442 443 - const: zcmop 444 description: 445 The standard Zcmop extension version 1.0, as ratified in commit 446 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 447 448 - const: zfa 449 description: 450 The standard Zfa extension for additional floating point 451 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 452 riscv-isa-manual. 453 454 - const: zfbfmin 455 description: 456 The standard Zfbfmin extension which provides minimal support for 457 16-bit half-precision brain floating-point instructions, as ratified 458 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 459 460 - const: zfh 461 description: 462 The standard Zfh extension for 16-bit half-precision binary 463 floating-point instructions, as ratified in commit 64074bc ("Update 464 version numbers for Zfh/Zfinx") of riscv-isa-manual. 465 466 - const: zfhmin 467 description: 468 The standard Zfhmin extension which provides minimal support for 469 16-bit half-precision binary floating-point instructions, as ratified 470 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 471 riscv-isa-manual. 472 473 - const: ziccamoa 474 description: 475 The standard Ziccamoa extension for main memory (cacheability and 476 coherence) must support all atomics in A, as ratified in RISC-V 477 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 478 ratified state.") 479 480 - const: ziccif 481 description: 482 The standard Ziccif extension for main memory (cacheability and 483 coherence) instruction fetch atomicity, as ratified in RISC-V 484 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 485 ratified state.") 486 487 - const: zicclsm 488 description: 489 The standard Zicclsm extension for main memory (cacheability and 490 coherence) must support misaligned loads and stores, as ratified 491 in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated 492 to ratified state.") 493 494 - const: ziccrse 495 description: 496 The standard Ziccrse extension which provides forward progress 497 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 498 ("Updated to ratified state.") of the riscv profiles specification. 499 500 - const: zilsd 501 description: 502 The standard Zilsd extension which provides support for aligned 503 register-pair load and store operations in 32-bit instruction 504 encodings, as ratified in commit f88abf1 ("Integrating 505 load/store pair for RV32 with the main manual") of riscv-isa-manual. 506 507 - const: zclsd 508 description: 509 The Zclsd extension implements the compressed (16-bit) version of the 510 Load/Store Pair for RV32. As with Zilsd, this extension was ratified 511 in commit f88abf1 ("Integrating load/store pair for RV32 with the 512 main manual") of riscv-isa-manual. 513 514 - const: zk 515 description: 516 The standard Zk Standard Scalar cryptography extension as ratified 517 in version 1.0 of RISC-V Cryptography Extensions Volume I 518 specification. 519 520 - const: zkn 521 description: 522 The standard Zkn NIST algorithm suite extensions as ratified in 523 version 1.0 of RISC-V Cryptography Extensions Volume I 524 specification. 525 526 - const: zknd 527 description: | 528 The standard Zknd for NIST suite: AES decryption instructions as 529 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 530 specification. 531 532 - const: zkne 533 description: | 534 The standard Zkne for NIST suite: AES encryption instructions as 535 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 536 specification. 537 538 - const: zknh 539 description: | 540 The standard Zknh for NIST suite: hash function instructions as 541 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 542 specification. 543 544 - const: zkr 545 description: 546 The standard Zkr entropy source extension as ratified in version 547 1.0 of RISC-V Cryptography Extensions Volume I specification. 548 This string being present means that the CSR associated to this 549 extension is accessible at the privilege level to which that 550 device-tree has been provided. 551 552 - const: zks 553 description: 554 The standard Zks ShangMi algorithm suite extensions as ratified in 555 version 1.0 of RISC-V Cryptography Extensions Volume I 556 specification. 557 558 - const: zksed 559 description: | 560 The standard Zksed for ShangMi suite: SM4 block cipher instructions 561 as ratified in version 1.0 of RISC-V Cryptography Extensions 562 Volume I specification. 563 564 - const: zksh 565 description: | 566 The standard Zksh for ShangMi suite: SM3 hash function instructions 567 as ratified in version 1.0 of RISC-V Cryptography Extensions 568 Volume I specification. 569 570 - const: zkt 571 description: 572 The standard Zkt for data independent execution latency as ratified 573 in version 1.0 of RISC-V Cryptography Extensions Volume I 574 specification. 575 576 - const: zicbom 577 description: 578 The standard Zicbom extension for base cache management operations as 579 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 580 581 - const: zicbop 582 description: 583 The standard Zicbop extension for cache-block prefetch instructions 584 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 585 riscv-CMOs. 586 587 - const: zicboz 588 description: 589 The standard Zicboz extension for cache-block zeroing as ratified 590 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 591 592 - const: zicntr 593 description: 594 The standard Zicntr extension for base counters and timers, as 595 ratified in the 20191213 version of the unprivileged ISA 596 specification. 597 598 - const: zicond 599 description: 600 The standard Zicond extension for conditional arithmetic and 601 conditional-select/move operations as ratified in commit 95cf1f9 602 ("Add changes requested by Ved during signoff") of riscv-zicond. 603 604 - const: zicsr 605 description: | 606 The standard Zicsr extension for control and status register 607 instructions, as ratified in the 20191213 version of the 608 unprivileged ISA specification. 609 610 This does not include Chapter 10, "Counters", which documents 611 special case read-only CSRs, that were moved into the Zicntr and 612 Zihpm extensions after the ratification of the 20191213 version of 613 the unprivileged specification. 614 615 - const: zifencei 616 description: 617 The standard Zifencei extension for instruction-fetch fence, as 618 ratified in the 20191213 version of the unprivileged ISA 619 specification. 620 621 - const: zihintpause 622 description: 623 The standard Zihintpause extension for pause hints, as ratified in 624 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 625 626 - const: zihintntl 627 description: 628 The standard Zihintntl extension for non-temporal locality hints, as 629 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 630 riscv-isa-manual. 631 632 - const: zihpm 633 description: 634 The standard Zihpm extension for hardware performance counters, as 635 ratified in the 20191213 version of the unprivileged ISA 636 specification. 637 638 - const: zimop 639 description: 640 The standard Zimop extension version 1.0, as ratified in commit 641 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 642 643 - const: ztso 644 description: 645 The standard Ztso extension for total store ordering, as ratified 646 in commit 2e5236 ("Ztso is now ratified.") of the 647 riscv-isa-manual. 648 649 - const: zvbb 650 description: 651 The standard Zvbb extension for vectored basic bit-manipulation 652 instructions, as ratified in commit 56ed795 ("Update 653 riscv-crypto-spec-vector.adoc") of riscv-crypto. 654 655 - const: zvbc 656 description: 657 The standard Zvbc extension for vectored carryless multiplication 658 instructions, as ratified in commit 56ed795 ("Update 659 riscv-crypto-spec-vector.adoc") of riscv-crypto. 660 661 - const: zve32f 662 description: 663 The standard Zve32f extension for embedded processors, as ratified 664 in commit 6f702a2 ("Vector extensions are now ratified") of 665 riscv-v-spec. 666 667 - const: zve32x 668 description: 669 The standard Zve32x extension for embedded processors, as ratified 670 in commit 6f702a2 ("Vector extensions are now ratified") of 671 riscv-v-spec. 672 673 - const: zve64d 674 description: 675 The standard Zve64d extension for embedded processors, as ratified 676 in commit 6f702a2 ("Vector extensions are now ratified") of 677 riscv-v-spec. 678 679 - const: zve64f 680 description: 681 The standard Zve64f extension for embedded processors, as ratified 682 in commit 6f702a2 ("Vector extensions are now ratified") of 683 riscv-v-spec. 684 685 - const: zve64x 686 description: 687 The standard Zve64x extension for embedded processors, as ratified 688 in commit 6f702a2 ("Vector extensions are now ratified") of 689 riscv-v-spec. 690 691 - const: zvfbfmin 692 description: 693 The standard Zvfbfmin extension for minimal support for vectored 694 16-bit half-precision brain floating-point instructions, as ratified 695 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 696 697 - const: zvfbfwma 698 description: 699 The standard Zvfbfwma extension for vectored half-precision brain 700 floating-point widening multiply-accumulate instructions, as ratified 701 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 702 703 - const: zvfh 704 description: 705 The standard Zvfh extension for vectored half-precision 706 floating-point instructions, as ratified in commit e2ccd05 707 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 708 709 - const: zvfhmin 710 description: 711 The standard Zvfhmin extension for vectored minimal half-precision 712 floating-point instructions, as ratified in commit e2ccd05 713 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 714 715 - const: zvkb 716 description: 717 The standard Zvkb extension for vector cryptography bit-manipulation 718 instructions, as ratified in commit 56ed795 ("Update 719 riscv-crypto-spec-vector.adoc") of riscv-crypto. 720 721 - const: zvkg 722 description: 723 The standard Zvkg extension for vector GCM/GMAC instructions, as 724 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 725 of riscv-crypto. 726 727 - const: zvkn 728 description: 729 The standard Zvkn extension for NIST algorithm suite instructions, as 730 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 731 of riscv-crypto. 732 733 - const: zvknc 734 description: 735 The standard Zvknc extension for NIST algorithm suite with carryless 736 multiply instructions, as ratified in commit 56ed795 ("Update 737 riscv-crypto-spec-vector.adoc") of riscv-crypto. 738 739 - const: zvkned 740 description: 741 The standard Zvkned extension for Vector AES block cipher 742 instructions, as ratified in commit 56ed795 ("Update 743 riscv-crypto-spec-vector.adoc") of riscv-crypto. 744 745 - const: zvkng 746 description: 747 The standard Zvkng extension for NIST algorithm suite with GCM 748 instructions, as ratified in commit 56ed795 ("Update 749 riscv-crypto-spec-vector.adoc") of riscv-crypto. 750 751 - const: zvknha 752 description: | 753 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 754 hash (SHA-256 only) instructions, as ratified in commit 755 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 756 757 - const: zvknhb 758 description: | 759 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 760 hash (SHA-256 and SHA-512) instructions, as ratified in commit 761 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 762 763 - const: zvks 764 description: 765 The standard Zvks extension for ShangMi algorithm suite 766 instructions, as ratified in commit 56ed795 ("Update 767 riscv-crypto-spec-vector.adoc") of riscv-crypto. 768 769 - const: zvksc 770 description: 771 The standard Zvksc extension for ShangMi algorithm suite with 772 carryless multiplication instructions, as ratified in commit 56ed795 773 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 774 775 - const: zvksed 776 description: | 777 The standard Zvksed extension for ShangMi suite: SM4 block cipher 778 instructions, as ratified in commit 56ed795 ("Update 779 riscv-crypto-spec-vector.adoc") of riscv-crypto. 780 781 - const: zvksh 782 description: | 783 The standard Zvksh extension for ShangMi suite: SM3 secure hash 784 instructions, as ratified in commit 56ed795 ("Update 785 riscv-crypto-spec-vector.adoc") of riscv-crypto. 786 787 - const: zvksg 788 description: 789 The standard Zvksg extension for ShangMi algorithm suite with GCM 790 instructions, as ratified in commit 56ed795 ("Update 791 riscv-crypto-spec-vector.adoc") of riscv-crypto. 792 793 - const: zvkt 794 description: 795 The standard Zvkt extension for vector data-independent execution 796 latency, as ratified in commit 56ed795 ("Update 797 riscv-crypto-spec-vector.adoc") of riscv-crypto. 798 799 # vendor extensions, each extension sorted alphanumerically under the 800 # vendor they belong to. Vendors are sorted alphanumerically as well. 801 802 # Andes 803 - const: xandespmu 804 description: 805 The Andes Technology performance monitor extension for counter overflow 806 and privilege mode filtering. For more details, see Counter Related 807 Registers in the AX45MP datasheet. 808 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 809 810 # MIPS 811 - const: xmipsexectl 812 description: 813 The MIPS extension for execution control as documented in 814 https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf 815 816 # SiFive 817 - const: xsfcease 818 description: 819 SiFive CEASE Instruction Extensions Specification. 820 See more details in 821 https://www.sifive.com/document-file/freedom-u740-c000-manual 822 823 - const: xsfcflushdlone 824 description: 825 SiFive L1D Cache Flush Instruction Extensions Specification. 826 See more details in 827 https://www.sifive.com/document-file/freedom-u740-c000-manual 828 829 - const: xsfpgflushdlone 830 description: 831 SiFive PGFLUSH Instruction Extensions for the power management. The 832 CPU will flush the L1D and enter the cease state after executing 833 the instruction. 834 835 - const: xsfvqmaccdod 836 description: 837 SiFive Int8 Matrix Multiplication Extensions Specification. 838 See more details in 839 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 840 841 - const: xsfvqmaccqoq 842 description: 843 SiFive Int8 Matrix Multiplication Extensions Specification. 844 See more details in 845 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 846 847 - const: xsfvfnrclipxfqf 848 description: 849 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. 850 See more details in 851 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions 852 853 - const: xsfvfwmaccqqq 854 description: 855 SiFive Matrix Multiply Accumulate Instruction Extensions Specification. 856 See more details in 857 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction 858 859 # T-HEAD 860 - const: xtheadvector 861 description: 862 The T-HEAD specific 0.7.1 vector implementation as written in 863 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 864 865 allOf: 866 - if: 867 contains: 868 const: d 869 then: 870 contains: 871 const: f 872 # B comprises Zba, Zbb, and Zbs 873 - if: 874 contains: 875 const: b 876 then: 877 allOf: 878 - contains: 879 const: zba 880 - contains: 881 const: zbb 882 - contains: 883 const: zbs 884 # Zba, Zbb, Zbs together require B 885 - if: 886 allOf: 887 - contains: 888 const: zba 889 - contains: 890 const: zbb 891 - contains: 892 const: zbs 893 then: 894 contains: 895 const: b 896 # Za64rs and Ziccrse depend on Zalrsc or A 897 - if: 898 contains: 899 anyOf: 900 - const: za64rs 901 - const: ziccrse 902 then: 903 oneOf: 904 - contains: 905 const: zalrsc 906 - contains: 907 const: a 908 # Zcb depends on Zca 909 - if: 910 contains: 911 const: zcb 912 then: 913 contains: 914 const: zca 915 # Zcd depends on Zca and D 916 - if: 917 contains: 918 const: zcd 919 then: 920 allOf: 921 - contains: 922 const: zca 923 - contains: 924 const: d 925 # Zcf depends on Zca and F 926 - if: 927 contains: 928 const: zcf 929 then: 930 allOf: 931 - contains: 932 const: zca 933 - contains: 934 const: f 935 # Zcmop depends on Zca 936 - if: 937 contains: 938 const: zcmop 939 then: 940 contains: 941 const: zca 942 # Zfbfmin depends on F 943 - if: 944 contains: 945 const: zfbfmin 946 then: 947 contains: 948 const: f 949 # Ziccamoa depends on Zaamo or A 950 - if: 951 contains: 952 const: ziccamoa 953 then: 954 oneOf: 955 - contains: 956 const: zaamo 957 - contains: 958 const: a 959 # Zvfbfmin depends on V or Zve32f 960 - if: 961 contains: 962 const: zvfbfmin 963 then: 964 oneOf: 965 - contains: 966 const: v 967 - contains: 968 const: zve32f 969 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 970 - if: 971 contains: 972 const: zvfbfwma 973 then: 974 allOf: 975 - contains: 976 const: zfbfmin 977 - contains: 978 const: zvfbfmin 979 # Zacas depends on Zaamo 980 - if: 981 contains: 982 const: zacas 983 then: 984 contains: 985 const: zaamo 986 987 - if: 988 contains: 989 const: zve32x 990 then: 991 contains: 992 const: zicsr 993 994 - if: 995 contains: 996 const: zve32f 997 then: 998 allOf: 999 - contains: 1000 const: f 1001 - contains: 1002 const: zve32x 1003 1004 - if: 1005 contains: 1006 const: zve64x 1007 then: 1008 contains: 1009 const: zve32x 1010 1011 - if: 1012 contains: 1013 const: zve64f 1014 then: 1015 allOf: 1016 - contains: 1017 const: f 1018 - contains: 1019 const: zve32f 1020 - contains: 1021 const: zve64x 1022 1023 - if: 1024 contains: 1025 const: zve64d 1026 then: 1027 allOf: 1028 - contains: 1029 const: d 1030 - contains: 1031 const: zve64f 1032 1033 - if: 1034 contains: 1035 anyOf: 1036 - const: zvbc 1037 - const: zvkn 1038 - const: zvknc 1039 - const: zvkng 1040 - const: zvknhb 1041 - const: zvksc 1042 then: 1043 contains: 1044 anyOf: 1045 - const: v 1046 - const: zve64x 1047 1048 - if: 1049 contains: 1050 anyOf: 1051 - const: zvbb 1052 - const: zvkb 1053 - const: zvkg 1054 - const: zvkned 1055 - const: zvknha 1056 - const: zvksed 1057 - const: zvksh 1058 - const: zvks 1059 - const: zvkt 1060 then: 1061 contains: 1062 anyOf: 1063 - const: v 1064 - const: zve32x 1065 # Zclsd depends on Zilsd and Zca 1066 - if: 1067 contains: 1068 anyOf: 1069 - const: zclsd 1070 then: 1071 contains: 1072 allOf: 1073 - const: zilsd 1074 - const: zca 1075 1076allOf: 1077 # Zcf extension does not exist on rv64 1078 - if: 1079 properties: 1080 riscv,isa-extensions: 1081 contains: 1082 const: zcf 1083 riscv,isa-base: 1084 contains: 1085 const: rv64i 1086 then: 1087 properties: 1088 riscv,isa-extensions: 1089 not: 1090 contains: 1091 const: zcf 1092 # Zilsd extension does not exist on rv64 1093 - if: 1094 properties: 1095 riscv,isa-base: 1096 contains: 1097 const: rv64i 1098 then: 1099 properties: 1100 riscv,isa-extensions: 1101 not: 1102 contains: 1103 const: zilsd 1104 1105additionalProperties: true 1106... 1107