1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smmpm 132 description: | 133 The standard Smmpm extension for M-mode pointer masking as 134 ratified at commit d70011dde6c2 ("Update to ratified state") 135 of riscv-j-extension. 136 137 - const: smnpm 138 description: | 139 The standard Smnpm extension for next-mode pointer masking as 140 ratified at commit d70011dde6c2 ("Update to ratified state") 141 of riscv-j-extension. 142 143 - const: smstateen 144 description: | 145 The standard Smstateen extension for controlling access to CSRs 146 added by other RISC-V extensions in H/S/VS/U/VU modes and as 147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 148 149 - const: ssaia 150 description: | 151 The standard Ssaia supervisor-level extension for the advanced 152 interrupt architecture for supervisor-mode-visible csr and 153 behavioural changes to interrupts as frozen at commit ccbddab 154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 155 156 - const: sscofpmf 157 description: | 158 The standard Sscofpmf supervisor-level extension for count overflow 159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 160 to manually trigger workflow. (#2)") of riscv-count-overflow. 161 162 - const: ssnpm 163 description: | 164 The standard Ssnpm extension for next-mode pointer masking as 165 ratified at commit d70011dde6c2 ("Update to ratified state") 166 of riscv-j-extension. 167 168 - const: sstc 169 description: | 170 The standard Sstc supervisor-level extension for time compare as 171 ratified at commit 3f9ed34 ("Add ability to manually trigger 172 workflow. (#2)") of riscv-time-compare. 173 174 - const: svade 175 description: | 176 The standard Svade supervisor-level extension for SW-managed PTE A/D 177 bit updates as ratified in the 20240213 version of the privileged 178 ISA specification. 179 180 Both Svade and Svadu extensions control the hardware behavior when 181 the PTE A/D bits need to be set. The default behavior for the four 182 possible combinations of these extensions in the device tree are: 183 1) Neither Svade nor Svadu present in DT => It is technically 184 unknown whether the platform uses Svade or Svadu. Supervisor 185 software should be prepared to handle either hardware updating 186 of the PTE A/D bits or page faults when they need updated. 187 2) Only Svade present in DT => Supervisor must assume Svade to be 188 always enabled. 189 3) Only Svadu present in DT => Supervisor must assume Svadu to be 190 always enabled. 191 4) Both Svade and Svadu present in DT => Supervisor must assume 192 Svadu turned-off at boot time. To use Svadu, supervisor must 193 explicitly enable it using the SBI FWFT extension. 194 195 - const: svadu 196 description: | 197 The standard Svadu supervisor-level extension for hardware updating 198 of PTE A/D bits as ratified in the 20240528 version of the 199 privileged ISA specification. Please refer to Svade dt-binding 200 description for more details. 201 202 - const: svinval 203 description: 204 The standard Svinval supervisor-level extension for fine-grained 205 address-translation cache invalidation as ratified in the 20191213 206 version of the privileged ISA specification. 207 208 - const: svnapot 209 description: 210 The standard Svnapot supervisor-level extensions for napot 211 translation contiguity as ratified in the 20191213 version of the 212 privileged ISA specification. 213 214 - const: svpbmt 215 description: 216 The standard Svpbmt supervisor-level extensions for page-based 217 memory types as ratified in the 20191213 version of the privileged 218 ISA specification. 219 220 - const: svvptc 221 description: 222 The standard Svvptc supervisor-level extension for 223 address-translation cache behaviour with respect to invalid entries 224 as ratified at commit 4a69197e5617 ("Update to ratified state") of 225 riscv-svvptc. 226 227 - const: zabha 228 description: | 229 The Zabha extension for Byte and Halfword Atomic Memory Operations 230 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 231 riscv-zabha. 232 233 - const: zacas 234 description: | 235 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 236 is supported as ratified at commit 5059e0ca641c ("update to 237 ratified") of the riscv-zacas. 238 239 - const: zawrs 240 description: | 241 The Zawrs extension for entering a low-power state or for trapping 242 to a hypervisor while waiting on a store to a memory location, as 243 ratified in commit 98918c844281 ("Merge pull request #1217 from 244 riscv/zawrs") of riscv-isa-manual. 245 246 - const: zba 247 description: | 248 The standard Zba bit-manipulation extension for address generation 249 acceleration instructions as ratified at commit 6d33919 ("Merge pull 250 request #158 from hirooih/clmul-fix-loop-end-condition") of 251 riscv-bitmanip. 252 253 - const: zbb 254 description: | 255 The standard Zbb bit-manipulation extension for basic bit-manipulation 256 as ratified at commit 6d33919 ("Merge pull request #158 from 257 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 258 259 - const: zbc 260 description: | 261 The standard Zbc bit-manipulation extension for carry-less 262 multiplication as ratified at commit 6d33919 ("Merge pull request 263 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 264 265 - const: zbkb 266 description: 267 The standard Zbkb bitmanip instructions for cryptography as ratified 268 in version 1.0 of RISC-V Cryptography Extensions Volume I 269 specification. 270 271 - const: zbkc 272 description: 273 The standard Zbkc carry-less multiply instructions as ratified 274 in version 1.0 of RISC-V Cryptography Extensions Volume I 275 specification. 276 277 - const: zbkx 278 description: 279 The standard Zbkx crossbar permutation instructions as ratified 280 in version 1.0 of RISC-V Cryptography Extensions Volume I 281 specification. 282 283 - const: zbs 284 description: | 285 The standard Zbs bit-manipulation extension for single-bit 286 instructions as ratified at commit 6d33919 ("Merge pull request #158 287 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 288 289 - const: zca 290 description: | 291 The Zca extension part of Zc* standard extensions for code size 292 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 293 RV64 as it contains no instructions") of riscv-code-size-reduction, 294 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 295 of zc.adoc to src tree."). 296 297 - const: zcb 298 description: | 299 The Zcb extension part of Zc* standard extensions for code size 300 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 301 RV64 as it contains no instructions") of riscv-code-size-reduction, 302 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 303 of zc.adoc to src tree."). 304 305 - const: zcd 306 description: | 307 The Zcd extension part of Zc* standard extensions for code size 308 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 309 RV64 as it contains no instructions") of riscv-code-size-reduction, 310 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 311 of zc.adoc to src tree."). 312 313 - const: zcf 314 description: | 315 The Zcf extension part of Zc* standard extensions for code size 316 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 317 RV64 as it contains no instructions") of riscv-code-size-reduction, 318 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 319 of zc.adoc to src tree."). 320 321 - const: zcmop 322 description: 323 The standard Zcmop extension version 1.0, as ratified in commit 324 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 325 326 - const: zfa 327 description: 328 The standard Zfa extension for additional floating point 329 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 330 riscv-isa-manual. 331 332 - const: zfbfmin 333 description: 334 The standard Zfbfmin extension which provides minimal support for 335 16-bit half-precision brain floating-point instructions, as ratified 336 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 337 338 - const: zfh 339 description: 340 The standard Zfh extension for 16-bit half-precision binary 341 floating-point instructions, as ratified in commit 64074bc ("Update 342 version numbers for Zfh/Zfinx") of riscv-isa-manual. 343 344 - const: zfhmin 345 description: 346 The standard Zfhmin extension which provides minimal support for 347 16-bit half-precision binary floating-point instructions, as ratified 348 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 349 riscv-isa-manual. 350 351 - const: ziccrse 352 description: 353 The standard Ziccrse extension which provides forward progress 354 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 355 ("Updated to ratified state.") of the riscv profiles specification. 356 357 - const: zk 358 description: 359 The standard Zk Standard Scalar cryptography extension as ratified 360 in version 1.0 of RISC-V Cryptography Extensions Volume I 361 specification. 362 363 - const: zkn 364 description: 365 The standard Zkn NIST algorithm suite extensions as ratified in 366 version 1.0 of RISC-V Cryptography Extensions Volume I 367 specification. 368 369 - const: zknd 370 description: | 371 The standard Zknd for NIST suite: AES decryption instructions as 372 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 373 specification. 374 375 - const: zkne 376 description: | 377 The standard Zkne for NIST suite: AES encryption instructions as 378 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 379 specification. 380 381 - const: zknh 382 description: | 383 The standard Zknh for NIST suite: hash function instructions as 384 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 385 specification. 386 387 - const: zkr 388 description: 389 The standard Zkr entropy source extension as ratified in version 390 1.0 of RISC-V Cryptography Extensions Volume I specification. 391 This string being present means that the CSR associated to this 392 extension is accessible at the privilege level to which that 393 device-tree has been provided. 394 395 - const: zks 396 description: 397 The standard Zks ShangMi algorithm suite extensions as ratified in 398 version 1.0 of RISC-V Cryptography Extensions Volume I 399 specification. 400 401 - const: zksed 402 description: | 403 The standard Zksed for ShangMi suite: SM4 block cipher instructions 404 as ratified in version 1.0 of RISC-V Cryptography Extensions 405 Volume I specification. 406 407 - const: zksh 408 description: | 409 The standard Zksh for ShangMi suite: SM3 hash function instructions 410 as ratified in version 1.0 of RISC-V Cryptography Extensions 411 Volume I specification. 412 413 - const: zkt 414 description: 415 The standard Zkt for data independent execution latency as ratified 416 in version 1.0 of RISC-V Cryptography Extensions Volume I 417 specification. 418 419 - const: zicbom 420 description: 421 The standard Zicbom extension for base cache management operations as 422 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 423 424 - const: zicbop 425 description: 426 The standard Zicbop extension for cache-block prefetch instructions 427 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 428 riscv-CMOs. 429 430 - const: zicboz 431 description: 432 The standard Zicboz extension for cache-block zeroing as ratified 433 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 434 435 - const: zicntr 436 description: 437 The standard Zicntr extension for base counters and timers, as 438 ratified in the 20191213 version of the unprivileged ISA 439 specification. 440 441 - const: zicond 442 description: 443 The standard Zicond extension for conditional arithmetic and 444 conditional-select/move operations as ratified in commit 95cf1f9 445 ("Add changes requested by Ved during signoff") of riscv-zicond. 446 447 - const: zicsr 448 description: | 449 The standard Zicsr extension for control and status register 450 instructions, as ratified in the 20191213 version of the 451 unprivileged ISA specification. 452 453 This does not include Chapter 10, "Counters", which documents 454 special case read-only CSRs, that were moved into the Zicntr and 455 Zihpm extensions after the ratification of the 20191213 version of 456 the unprivileged specification. 457 458 - const: zifencei 459 description: 460 The standard Zifencei extension for instruction-fetch fence, as 461 ratified in the 20191213 version of the unprivileged ISA 462 specification. 463 464 - const: zihintpause 465 description: 466 The standard Zihintpause extension for pause hints, as ratified in 467 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 468 469 - const: zihintntl 470 description: 471 The standard Zihintntl extension for non-temporal locality hints, as 472 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 473 riscv-isa-manual. 474 475 - const: zihpm 476 description: 477 The standard Zihpm extension for hardware performance counters, as 478 ratified in the 20191213 version of the unprivileged ISA 479 specification. 480 481 - const: zimop 482 description: 483 The standard Zimop extension version 1.0, as ratified in commit 484 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 485 486 - const: ztso 487 description: 488 The standard Ztso extension for total store ordering, as ratified 489 in commit 2e5236 ("Ztso is now ratified.") of the 490 riscv-isa-manual. 491 492 - const: zvbb 493 description: 494 The standard Zvbb extension for vectored basic bit-manipulation 495 instructions, as ratified in commit 56ed795 ("Update 496 riscv-crypto-spec-vector.adoc") of riscv-crypto. 497 498 - const: zvbc 499 description: 500 The standard Zvbc extension for vectored carryless multiplication 501 instructions, as ratified in commit 56ed795 ("Update 502 riscv-crypto-spec-vector.adoc") of riscv-crypto. 503 504 - const: zve32f 505 description: 506 The standard Zve32f extension for embedded processors, as ratified 507 in commit 6f702a2 ("Vector extensions are now ratified") of 508 riscv-v-spec. 509 510 - const: zve32x 511 description: 512 The standard Zve32x extension for embedded processors, as ratified 513 in commit 6f702a2 ("Vector extensions are now ratified") of 514 riscv-v-spec. 515 516 - const: zve64d 517 description: 518 The standard Zve64d extension for embedded processors, as ratified 519 in commit 6f702a2 ("Vector extensions are now ratified") of 520 riscv-v-spec. 521 522 - const: zve64f 523 description: 524 The standard Zve64f extension for embedded processors, as ratified 525 in commit 6f702a2 ("Vector extensions are now ratified") of 526 riscv-v-spec. 527 528 - const: zve64x 529 description: 530 The standard Zve64x extension for embedded processors, as ratified 531 in commit 6f702a2 ("Vector extensions are now ratified") of 532 riscv-v-spec. 533 534 - const: zvfbfmin 535 description: 536 The standard Zvfbfmin extension for minimal support for vectored 537 16-bit half-precision brain floating-point instructions, as ratified 538 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 539 540 - const: zvfbfwma 541 description: 542 The standard Zvfbfwma extension for vectored half-precision brain 543 floating-point widening multiply-accumulate instructions, as ratified 544 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 545 546 - const: zvfh 547 description: 548 The standard Zvfh extension for vectored half-precision 549 floating-point instructions, as ratified in commit e2ccd05 550 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 551 552 - const: zvfhmin 553 description: 554 The standard Zvfhmin extension for vectored minimal half-precision 555 floating-point instructions, as ratified in commit e2ccd05 556 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 557 558 - const: zvkb 559 description: 560 The standard Zvkb extension for vector cryptography bit-manipulation 561 instructions, as ratified in commit 56ed795 ("Update 562 riscv-crypto-spec-vector.adoc") of riscv-crypto. 563 564 - const: zvkg 565 description: 566 The standard Zvkg extension for vector GCM/GMAC instructions, as 567 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 568 of riscv-crypto. 569 570 - const: zvkn 571 description: 572 The standard Zvkn extension for NIST algorithm suite instructions, as 573 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 574 of riscv-crypto. 575 576 - const: zvknc 577 description: 578 The standard Zvknc extension for NIST algorithm suite with carryless 579 multiply instructions, as ratified in commit 56ed795 ("Update 580 riscv-crypto-spec-vector.adoc") of riscv-crypto. 581 582 - const: zvkned 583 description: 584 The standard Zvkned extension for Vector AES block cipher 585 instructions, as ratified in commit 56ed795 ("Update 586 riscv-crypto-spec-vector.adoc") of riscv-crypto. 587 588 - const: zvkng 589 description: 590 The standard Zvkng extension for NIST algorithm suite with GCM 591 instructions, as ratified in commit 56ed795 ("Update 592 riscv-crypto-spec-vector.adoc") of riscv-crypto. 593 594 - const: zvknha 595 description: | 596 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 597 hash (SHA-256 only) instructions, as ratified in commit 598 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 599 600 - const: zvknhb 601 description: | 602 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 603 hash (SHA-256 and SHA-512) instructions, as ratified in commit 604 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 605 606 - const: zvks 607 description: 608 The standard Zvks extension for ShangMi algorithm suite 609 instructions, as ratified in commit 56ed795 ("Update 610 riscv-crypto-spec-vector.adoc") of riscv-crypto. 611 612 - const: zvksc 613 description: 614 The standard Zvksc extension for ShangMi algorithm suite with 615 carryless multiplication instructions, as ratified in commit 56ed795 616 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 617 618 - const: zvksed 619 description: | 620 The standard Zvksed extension for ShangMi suite: SM4 block cipher 621 instructions, as ratified in commit 56ed795 ("Update 622 riscv-crypto-spec-vector.adoc") of riscv-crypto. 623 624 - const: zvksh 625 description: | 626 The standard Zvksh extension for ShangMi suite: SM3 secure hash 627 instructions, as ratified in commit 56ed795 ("Update 628 riscv-crypto-spec-vector.adoc") of riscv-crypto. 629 630 - const: zvksg 631 description: 632 The standard Zvksg extension for ShangMi algorithm suite with GCM 633 instructions, as ratified in commit 56ed795 ("Update 634 riscv-crypto-spec-vector.adoc") of riscv-crypto. 635 636 - const: zvkt 637 description: 638 The standard Zvkt extension for vector data-independent execution 639 latency, as ratified in commit 56ed795 ("Update 640 riscv-crypto-spec-vector.adoc") of riscv-crypto. 641 642 # vendor extensions, each extension sorted alphanumerically under the 643 # vendor they belong to. Vendors are sorted alphanumerically as well. 644 645 # Andes 646 - const: xandespmu 647 description: 648 The Andes Technology performance monitor extension for counter overflow 649 and privilege mode filtering. For more details, see Counter Related 650 Registers in the AX45MP datasheet. 651 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 652 653 # T-HEAD 654 - const: xtheadvector 655 description: 656 The T-HEAD specific 0.7.1 vector implementation as written in 657 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 658 659 allOf: 660 # Zcb depends on Zca 661 - if: 662 contains: 663 const: zcb 664 then: 665 contains: 666 const: zca 667 # Zcd depends on Zca and D 668 - if: 669 contains: 670 const: zcd 671 then: 672 allOf: 673 - contains: 674 const: zca 675 - contains: 676 const: d 677 # Zcf depends on Zca and F 678 - if: 679 contains: 680 const: zcf 681 then: 682 allOf: 683 - contains: 684 const: zca 685 - contains: 686 const: f 687 # Zcmop depends on Zca 688 - if: 689 contains: 690 const: zcmop 691 then: 692 contains: 693 const: zca 694 # Zfbfmin depends on F 695 - if: 696 contains: 697 const: zfbfmin 698 then: 699 contains: 700 const: f 701 # Zvfbfmin depends on V or Zve32f 702 - if: 703 contains: 704 const: zvfbfmin 705 then: 706 oneOf: 707 - contains: 708 const: v 709 - contains: 710 const: zve32f 711 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 712 - if: 713 contains: 714 const: zvfbfwma 715 then: 716 allOf: 717 - contains: 718 const: zfbfmin 719 - contains: 720 const: zvfbfmin 721 722allOf: 723 # Zcf extension does not exist on rv64 724 - if: 725 properties: 726 riscv,isa-extensions: 727 contains: 728 const: zcf 729 riscv,isa-base: 730 contains: 731 const: rv64i 732 then: 733 properties: 734 riscv,isa-extensions: 735 not: 736 contains: 737 const: zcf 738 739additionalProperties: true 740... 741