xref: /linux/Documentation/devicetree/bindings/riscv/extensions.yaml (revision 2eff01ee2881becc9daaa0d53477ec202136b1f4)
1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/riscv/extensions.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V ISA extensions
8
9maintainers:
10  - Paul Walmsley <paul.walmsley@sifive.com>
11  - Palmer Dabbelt <palmer@sifive.com>
12  - Conor Dooley <conor@kernel.org>
13
14description: |
15  RISC-V has a large number of extensions, some of which are "standard"
16  extensions, meaning they are ratified by RISC-V International, and others
17  are "vendor" extensions.
18  This document defines properties that indicate whether a hart supports a
19  given extension.
20
21  Once a standard extension has been ratified, no changes in behaviour can be
22  made without the creation of a new extension.
23  The properties for standard extensions therefore map to their originally
24  ratified states, with the exception of the I, Zicntr & Zihpm extensions.
25  See the "i" property for more information.
26
27select:
28  properties:
29    compatible:
30      contains:
31        const: riscv
32
33properties:
34  riscv,isa:
35    description:
36      Identifies the specific RISC-V instruction set architecture
37      supported by the hart.  These are documented in the RISC-V
38      User-Level ISA document, available from
39      https://riscv.org/specifications/
40
41      Due to revisions of the ISA specification, some deviations
42      have arisen over time.
43      Notably, riscv,isa was defined prior to the creation of the
44      Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
45      implies "zicntr_zicsr_zifencei_zihpm".
46
47      While the isa strings in ISA specification are case
48      insensitive, letters in the riscv,isa string must be all
49      lowercase.
50    $ref: /schemas/types.yaml#/definitions/string
51    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
52    deprecated: true
53
54  riscv,isa-base:
55    description:
56      The base ISA implemented by this hart, as described by the 20191213
57      version of the unprivileged ISA specification.
58    enum:
59      - rv32i
60      - rv64i
61
62  riscv,isa-extensions:
63    $ref: /schemas/types.yaml#/definitions/string-array
64    minItems: 1
65    description: Extensions supported by the hart.
66    items:
67      anyOf:
68        # single letter extensions, in canonical order
69        - const: i
70          description: |
71            The base integer instruction set, as ratified in the 20191213
72            version of the unprivileged ISA specification.
73
74            This does not include Chapter 10, "Counters", which was moved into
75            the Zicntr and Zihpm extensions after the ratification of the
76            20191213 version of the unprivileged specification.
77
78        - const: m
79          description:
80            The standard M extension for integer multiplication and division, as
81            ratified in the 20191213 version of the unprivileged ISA
82            specification.
83
84        - const: a
85          description:
86            The standard A extension for atomic instructions, as ratified in the
87            20191213 version of the unprivileged ISA specification.
88
89        - const: f
90          description:
91            The standard F extension for single-precision floating point, as
92            ratified in the 20191213 version of the unprivileged ISA
93            specification.
94
95        - const: d
96          description:
97            The standard D extension for double-precision floating-point, as
98            ratified in the 20191213 version of the unprivileged ISA
99            specification.
100
101        - const: q
102          description:
103            The standard Q extension for quad-precision floating-point, as
104            ratified in the 20191213 version of the unprivileged ISA
105            specification.
106
107        - const: c
108          description:
109            The standard C extension for compressed instructions, as ratified in
110            the 20191213 version of the unprivileged ISA specification.
111
112        - const: v
113          description:
114            The standard V extension for vector operations, as ratified
115            in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116            encoding") of the riscv-v-spec.
117
118        - const: h
119          description:
120            The standard H extension for hypervisors as ratified in the 20191213
121            version of the privileged ISA specification.
122
123        # multi-letter extensions, sorted alphanumerically
124        - const: smaia
125          description: |
126            The standard Smaia supervisor-level extension for the advanced
127            interrupt architecture for machine-mode-visible csr and behavioural
128            changes to interrupts as frozen at commit ccbddab ("Merge pull
129            request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
130
131        - const: smmpm
132          description: |
133            The standard Smmpm extension for M-mode pointer masking as
134            ratified at commit d70011dde6c2 ("Update to ratified state")
135            of riscv-j-extension.
136
137        - const: smnpm
138          description: |
139            The standard Smnpm extension for next-mode pointer masking as
140            ratified at commit d70011dde6c2 ("Update to ratified state")
141            of riscv-j-extension.
142
143        - const: smstateen
144          description: |
145            The standard Smstateen extension for controlling access to CSRs
146            added by other RISC-V extensions in H/S/VS/U/VU modes and as
147            ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
148
149        - const: ssaia
150          description: |
151            The standard Ssaia supervisor-level extension for the advanced
152            interrupt architecture for supervisor-mode-visible csr and
153            behavioural changes to interrupts as frozen at commit ccbddab
154            ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
155
156        - const: sscofpmf
157          description: |
158            The standard Sscofpmf supervisor-level extension for count overflow
159            and mode-based filtering as ratified at commit 01d1df0 ("Add ability
160            to manually trigger workflow. (#2)") of riscv-count-overflow.
161
162        - const: ssnpm
163          description: |
164            The standard Ssnpm extension for next-mode pointer masking as
165            ratified at commit d70011dde6c2 ("Update to ratified state")
166            of riscv-j-extension.
167
168        - const: sstc
169          description: |
170            The standard Sstc supervisor-level extension for time compare as
171            ratified at commit 3f9ed34 ("Add ability to manually trigger
172            workflow. (#2)") of riscv-time-compare.
173
174        - const: svinval
175          description:
176            The standard Svinval supervisor-level extension for fine-grained
177            address-translation cache invalidation as ratified in the 20191213
178            version of the privileged ISA specification.
179
180        - const: svnapot
181          description:
182            The standard Svnapot supervisor-level extensions for napot
183            translation contiguity as ratified in the 20191213 version of the
184            privileged ISA specification.
185
186        - const: svpbmt
187          description:
188            The standard Svpbmt supervisor-level extensions for page-based
189            memory types as ratified in the 20191213 version of the privileged
190            ISA specification.
191
192        - const: svvptc
193          description:
194            The standard Svvptc supervisor-level extension for
195            address-translation cache behaviour with respect to invalid entries
196            as ratified at commit 4a69197e5617 ("Update to ratified state") of
197            riscv-svvptc.
198
199        - const: zabha
200          description: |
201            The Zabha extension for Byte and Halfword Atomic Memory Operations
202            as ratified at commit 49f49c842ff9 ("Update to Rafified state") of
203            riscv-zabha.
204
205        - const: zacas
206          description: |
207            The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
208            is supported as ratified at commit 5059e0ca641c ("update to
209            ratified") of the riscv-zacas.
210
211        - const: zawrs
212          description: |
213            The Zawrs extension for entering a low-power state or for trapping
214            to a hypervisor while waiting on a store to a memory location, as
215            ratified in commit 98918c844281 ("Merge pull request #1217 from
216            riscv/zawrs") of riscv-isa-manual.
217
218        - const: zba
219          description: |
220            The standard Zba bit-manipulation extension for address generation
221            acceleration instructions as ratified at commit 6d33919 ("Merge pull
222            request #158 from hirooih/clmul-fix-loop-end-condition") of
223            riscv-bitmanip.
224
225        - const: zbb
226          description: |
227            The standard Zbb bit-manipulation extension for basic bit-manipulation
228            as ratified at commit 6d33919 ("Merge pull request #158 from
229            hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
230
231        - const: zbc
232          description: |
233            The standard Zbc bit-manipulation extension for carry-less
234            multiplication as ratified at commit 6d33919 ("Merge pull request
235            #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
236
237        - const: zbkb
238          description:
239            The standard Zbkb bitmanip instructions for cryptography as ratified
240            in version 1.0 of RISC-V Cryptography Extensions Volume I
241            specification.
242
243        - const: zbkc
244          description:
245            The standard Zbkc carry-less multiply instructions as ratified
246            in version 1.0 of RISC-V Cryptography Extensions Volume I
247            specification.
248
249        - const: zbkx
250          description:
251            The standard Zbkx crossbar permutation instructions as ratified
252            in version 1.0 of RISC-V Cryptography Extensions Volume I
253            specification.
254
255        - const: zbs
256          description: |
257            The standard Zbs bit-manipulation extension for single-bit
258            instructions as ratified at commit 6d33919 ("Merge pull request #158
259            from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
260
261        - const: zca
262          description: |
263            The Zca extension part of Zc* standard extensions for code size
264            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
265            RV64 as it contains no instructions") of riscv-code-size-reduction,
266            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
267            of zc.adoc to src tree.").
268
269        - const: zcb
270          description: |
271            The Zcb extension part of Zc* standard extensions for code size
272            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
273            RV64 as it contains no instructions") of riscv-code-size-reduction,
274            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
275            of zc.adoc to src tree.").
276
277        - const: zcd
278          description: |
279            The Zcd extension part of Zc* standard extensions for code size
280            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
281            RV64 as it contains no instructions") of riscv-code-size-reduction,
282            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
283            of zc.adoc to src tree.").
284
285        - const: zcf
286          description: |
287            The Zcf extension part of Zc* standard extensions for code size
288            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
289            RV64 as it contains no instructions") of riscv-code-size-reduction,
290            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
291            of zc.adoc to src tree.").
292
293        - const: zcmop
294          description:
295            The standard Zcmop extension version 1.0, as ratified in commit
296            c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
297
298        - const: zfa
299          description:
300            The standard Zfa extension for additional floating point
301            instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
302            riscv-isa-manual.
303
304        - const: zfh
305          description:
306            The standard Zfh extension for 16-bit half-precision binary
307            floating-point instructions, as ratified in commit 64074bc ("Update
308            version numbers for Zfh/Zfinx") of riscv-isa-manual.
309
310        - const: zfhmin
311          description:
312            The standard Zfhmin extension which provides minimal support for
313            16-bit half-precision binary floating-point instructions, as ratified
314            in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
315            riscv-isa-manual.
316
317        - const: ziccrse
318          description:
319            The standard Ziccrse extension which provides forward progress
320            guarantee on LR/SC sequences, as ratified in commit b1d806605f87
321            ("Updated to ratified state.") of the riscv profiles specification.
322
323        - const: zk
324          description:
325            The standard Zk Standard Scalar cryptography extension as ratified
326            in version 1.0 of RISC-V Cryptography Extensions Volume I
327            specification.
328
329        - const: zkn
330          description:
331            The standard Zkn NIST algorithm suite extensions as ratified in
332            version 1.0 of RISC-V Cryptography Extensions Volume I
333            specification.
334
335        - const: zknd
336          description: |
337            The standard Zknd for NIST suite: AES decryption instructions as
338            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
339            specification.
340
341        - const: zkne
342          description: |
343            The standard Zkne for NIST suite: AES encryption instructions as
344            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
345            specification.
346
347        - const: zknh
348          description: |
349            The standard Zknh for NIST suite: hash function instructions as
350            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
351            specification.
352
353        - const: zkr
354          description:
355            The standard Zkr entropy source extension as ratified in version
356            1.0 of RISC-V Cryptography Extensions Volume I specification.
357            This string being present means that the CSR associated to this
358            extension is accessible at the privilege level to which that
359            device-tree has been provided.
360
361        - const: zks
362          description:
363            The standard Zks ShangMi algorithm suite extensions as ratified in
364            version 1.0 of RISC-V Cryptography Extensions Volume I
365            specification.
366
367        - const: zksed
368          description: |
369            The standard Zksed for ShangMi suite: SM4 block cipher instructions
370            as ratified in version 1.0 of RISC-V Cryptography Extensions
371            Volume I specification.
372
373        - const: zksh
374          description: |
375            The standard Zksh for ShangMi suite: SM3 hash function instructions
376            as ratified in version 1.0 of RISC-V Cryptography Extensions
377            Volume I specification.
378
379        - const: zkt
380          description:
381            The standard Zkt for data independent execution latency as ratified
382            in version 1.0 of RISC-V Cryptography Extensions Volume I
383            specification.
384
385        - const: zicbom
386          description:
387            The standard Zicbom extension for base cache management operations as
388            ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
389
390        - const: zicbop
391          description:
392            The standard Zicbop extension for cache-block prefetch instructions
393            as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
394            riscv-CMOs.
395
396        - const: zicboz
397          description:
398            The standard Zicboz extension for cache-block zeroing as ratified
399            in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
400
401        - const: zicntr
402          description:
403            The standard Zicntr extension for base counters and timers, as
404            ratified in the 20191213 version of the unprivileged ISA
405            specification.
406
407        - const: zicond
408          description:
409            The standard Zicond extension for conditional arithmetic and
410            conditional-select/move operations as ratified in commit 95cf1f9
411            ("Add changes requested by Ved during signoff") of riscv-zicond.
412
413        - const: zicsr
414          description: |
415            The standard Zicsr extension for control and status register
416            instructions, as ratified in the 20191213 version of the
417            unprivileged ISA specification.
418
419            This does not include Chapter 10, "Counters", which documents
420            special case read-only CSRs, that were moved into the Zicntr and
421            Zihpm extensions after the ratification of the 20191213 version of
422            the unprivileged specification.
423
424        - const: zifencei
425          description:
426            The standard Zifencei extension for instruction-fetch fence, as
427            ratified in the 20191213 version of the unprivileged ISA
428            specification.
429
430        - const: zihintpause
431          description:
432            The standard Zihintpause extension for pause hints, as ratified in
433            commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
434
435        - const: zihintntl
436          description:
437            The standard Zihintntl extension for non-temporal locality hints, as
438            ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
439            riscv-isa-manual.
440
441        - const: zihpm
442          description:
443            The standard Zihpm extension for hardware performance counters, as
444            ratified in the 20191213 version of the unprivileged ISA
445            specification.
446
447        - const: zimop
448          description:
449            The standard Zimop extension version 1.0, as ratified in commit
450            58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
451
452        - const: ztso
453          description:
454            The standard Ztso extension for total store ordering, as ratified
455            in commit 2e5236 ("Ztso is now ratified.") of the
456            riscv-isa-manual.
457
458        - const: zvbb
459          description:
460            The standard Zvbb extension for vectored basic bit-manipulation
461            instructions, as ratified in commit 56ed795 ("Update
462            riscv-crypto-spec-vector.adoc") of riscv-crypto.
463
464        - const: zvbc
465          description:
466            The standard Zvbc extension for vectored carryless multiplication
467            instructions, as ratified in commit 56ed795 ("Update
468            riscv-crypto-spec-vector.adoc") of riscv-crypto.
469
470        - const: zve32f
471          description:
472            The standard Zve32f extension for embedded processors, as ratified
473            in commit 6f702a2 ("Vector extensions are now ratified") of
474            riscv-v-spec.
475
476        - const: zve32x
477          description:
478            The standard Zve32x extension for embedded processors, as ratified
479            in commit 6f702a2 ("Vector extensions are now ratified") of
480            riscv-v-spec.
481
482        - const: zve64d
483          description:
484            The standard Zve64d extension for embedded processors, as ratified
485            in commit 6f702a2 ("Vector extensions are now ratified") of
486            riscv-v-spec.
487
488        - const: zve64f
489          description:
490            The standard Zve64f extension for embedded processors, as ratified
491            in commit 6f702a2 ("Vector extensions are now ratified") of
492            riscv-v-spec.
493
494        - const: zve64x
495          description:
496            The standard Zve64x extension for embedded processors, as ratified
497            in commit 6f702a2 ("Vector extensions are now ratified") of
498            riscv-v-spec.
499
500        - const: zvfh
501          description:
502            The standard Zvfh extension for vectored half-precision
503            floating-point instructions, as ratified in commit e2ccd05
504            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
505
506        - const: zvfhmin
507          description:
508            The standard Zvfhmin extension for vectored minimal half-precision
509            floating-point instructions, as ratified in commit e2ccd05
510            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
511
512        - const: zvkb
513          description:
514            The standard Zvkb extension for vector cryptography bit-manipulation
515            instructions, as ratified in commit 56ed795 ("Update
516            riscv-crypto-spec-vector.adoc") of riscv-crypto.
517
518        - const: zvkg
519          description:
520            The standard Zvkg extension for vector GCM/GMAC instructions, as
521            ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
522            of riscv-crypto.
523
524        - const: zvkn
525          description:
526            The standard Zvkn extension for NIST algorithm suite instructions, as
527            ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
528            of riscv-crypto.
529
530        - const: zvknc
531          description:
532            The standard Zvknc extension for NIST algorithm suite with carryless
533            multiply instructions, as ratified in commit 56ed795 ("Update
534            riscv-crypto-spec-vector.adoc") of riscv-crypto.
535
536        - const: zvkned
537          description:
538            The standard Zvkned extension for Vector AES block cipher
539            instructions, as ratified in commit 56ed795 ("Update
540            riscv-crypto-spec-vector.adoc") of riscv-crypto.
541
542        - const: zvkng
543          description:
544            The standard Zvkng extension for NIST algorithm suite with GCM
545            instructions, as ratified in commit 56ed795 ("Update
546            riscv-crypto-spec-vector.adoc") of riscv-crypto.
547
548        - const: zvknha
549          description: |
550            The standard Zvknha extension for NIST suite: vector SHA-2 secure,
551            hash (SHA-256 only) instructions, as ratified in commit
552            56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
553
554        - const: zvknhb
555          description: |
556            The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
557            hash (SHA-256 and SHA-512) instructions, as ratified in commit
558            56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
559
560        - const: zvks
561          description:
562            The standard Zvks extension for ShangMi algorithm suite
563            instructions, as ratified in commit 56ed795 ("Update
564            riscv-crypto-spec-vector.adoc") of riscv-crypto.
565
566        - const: zvksc
567          description:
568            The standard Zvksc extension for ShangMi algorithm suite with
569            carryless multiplication instructions, as ratified in commit 56ed795
570            ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
571
572        - const: zvksed
573          description: |
574            The standard Zvksed extension for ShangMi suite: SM4 block cipher
575            instructions, as ratified in commit 56ed795 ("Update
576            riscv-crypto-spec-vector.adoc") of riscv-crypto.
577
578        - const: zvksh
579          description: |
580            The standard Zvksh extension for ShangMi suite: SM3 secure hash
581            instructions, as ratified in commit 56ed795 ("Update
582            riscv-crypto-spec-vector.adoc") of riscv-crypto.
583
584        - const: zvksg
585          description:
586            The standard Zvksg extension for ShangMi algorithm suite with GCM
587            instructions, as ratified in commit 56ed795 ("Update
588            riscv-crypto-spec-vector.adoc") of riscv-crypto.
589
590        - const: zvkt
591          description:
592            The standard Zvkt extension for vector data-independent execution
593            latency, as ratified in commit 56ed795 ("Update
594            riscv-crypto-spec-vector.adoc") of riscv-crypto.
595
596        - const: xandespmu
597          description:
598            The Andes Technology performance monitor extension for counter overflow
599            and privilege mode filtering. For more details, see Counter Related
600            Registers in the AX45MP datasheet.
601            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
602
603    allOf:
604      # Zcb depends on Zca
605      - if:
606          contains:
607            const: zcb
608        then:
609          contains:
610            const: zca
611      # Zcd depends on Zca and D
612      - if:
613          contains:
614            const: zcd
615        then:
616          allOf:
617            - contains:
618                const: zca
619            - contains:
620                const: d
621      # Zcf depends on Zca and F
622      - if:
623          contains:
624            const: zcf
625        then:
626          allOf:
627            - contains:
628                const: zca
629            - contains:
630                const: f
631      # Zcmop depends on Zca
632      - if:
633          contains:
634            const: zcmop
635        then:
636          contains:
637            const: zca
638
639allOf:
640  # Zcf extension does not exist on rv64
641  - if:
642      properties:
643        riscv,isa-extensions:
644          contains:
645            const: zcf
646        riscv,isa-base:
647          contains:
648            const: rv64i
649    then:
650      properties:
651        riscv,isa-extensions:
652          not:
653            contains:
654              const: zcf
655
656additionalProperties: true
657...
658