1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 - $ref: extensions.yaml 29 30properties: 31 compatible: 32 oneOf: 33 - items: 34 - enum: 35 - amd,mbv32 36 - andestech,ax45mp 37 - canaan,k210 38 - sifive,bullet0 39 - sifive,e5 40 - sifive,e7 41 - sifive,e71 42 - sifive,rocket0 43 - sifive,s7 44 - sifive,u5 45 - sifive,u54 46 - sifive,u7 47 - sifive,u74 48 - sifive,u74-mc 49 - thead,c906 50 - thead,c910 51 - thead,c920 52 - const: riscv 53 - items: 54 - enum: 55 - sifive,e51 56 - sifive,u54-mc 57 - const: sifive,rocket0 58 - const: riscv 59 - const: riscv # Simulator only 60 description: 61 Identifies that the hart uses the RISC-V instruction set 62 and identifies the type of the hart. 63 64 mmu-type: 65 description: 66 Identifies the largest MMU address translation mode supported by 67 this hart. These values originate from the RISC-V Privileged 68 Specification document, available from 69 https://riscv.org/specifications/ 70 $ref: /schemas/types.yaml#/definitions/string 71 enum: 72 - riscv,sv32 73 - riscv,sv39 74 - riscv,sv48 75 - riscv,sv57 76 - riscv,none 77 78 reg: 79 description: 80 The hart ID of this CPU node. 81 82 riscv,cbom-block-size: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 description: 85 The blocksize in bytes for the Zicbom cache operations. 86 87 riscv,cbop-block-size: 88 $ref: /schemas/types.yaml#/definitions/uint32 89 description: 90 The blocksize in bytes for the Zicbop cache operations. 91 92 riscv,cboz-block-size: 93 $ref: /schemas/types.yaml#/definitions/uint32 94 description: 95 The blocksize in bytes for the Zicboz cache operations. 96 97 # RISC-V has multiple properties for cache op block sizes as the sizes 98 # differ between individual CBO extensions 99 cache-op-block-size: false 100 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 101 timebase-frequency: false 102 103 interrupt-controller: 104 type: object 105 additionalProperties: false 106 description: Describes the CPU's local interrupt controller 107 108 properties: 109 '#interrupt-cells': 110 const: 1 111 112 compatible: 113 const: riscv,cpu-intc 114 115 interrupt-controller: true 116 117 required: 118 - '#interrupt-cells' 119 - compatible 120 - interrupt-controller 121 122 cpu-idle-states: 123 $ref: /schemas/types.yaml#/definitions/phandle-array 124 items: 125 maxItems: 1 126 description: | 127 List of phandles to idle state nodes supported 128 by this hart (see ./idle-states.yaml). 129 130 capacity-dmips-mhz: 131 description: 132 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 133 DMIPS/MHz, relative to highest capacity-dmips-mhz 134 in the system. 135 136anyOf: 137 - required: 138 - riscv,isa 139 - required: 140 - riscv,isa-base 141 142dependencies: 143 riscv,isa-base: [ "riscv,isa-extensions" ] 144 riscv,isa-extensions: [ "riscv,isa-base" ] 145 146required: 147 - interrupt-controller 148 149unevaluatedProperties: false 150 151examples: 152 - | 153 // Example 1: SiFive Freedom U540G Development Kit 154 cpus { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 timebase-frequency = <1000000>; 158 cpu@0 { 159 clock-frequency = <0>; 160 compatible = "sifive,rocket0", "riscv"; 161 device_type = "cpu"; 162 i-cache-block-size = <64>; 163 i-cache-sets = <128>; 164 i-cache-size = <16384>; 165 reg = <0>; 166 riscv,isa-base = "rv64i"; 167 riscv,isa-extensions = "i", "m", "a", "c"; 168 169 cpu_intc0: interrupt-controller { 170 #interrupt-cells = <1>; 171 compatible = "riscv,cpu-intc"; 172 interrupt-controller; 173 }; 174 }; 175 cpu@1 { 176 clock-frequency = <0>; 177 compatible = "sifive,rocket0", "riscv"; 178 d-cache-block-size = <64>; 179 d-cache-sets = <64>; 180 d-cache-size = <32768>; 181 d-tlb-sets = <1>; 182 d-tlb-size = <32>; 183 device_type = "cpu"; 184 i-cache-block-size = <64>; 185 i-cache-sets = <64>; 186 i-cache-size = <32768>; 187 i-tlb-sets = <1>; 188 i-tlb-size = <32>; 189 mmu-type = "riscv,sv39"; 190 reg = <1>; 191 tlb-split; 192 riscv,isa-base = "rv64i"; 193 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 194 195 cpu_intc1: interrupt-controller { 196 #interrupt-cells = <1>; 197 compatible = "riscv,cpu-intc"; 198 interrupt-controller; 199 }; 200 }; 201 }; 202 203 - | 204 // Example 2: Spike ISA Simulator with 1 Hart 205 cpus { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 cpu@0 { 209 device_type = "cpu"; 210 reg = <0>; 211 compatible = "riscv"; 212 mmu-type = "riscv,sv48"; 213 riscv,isa-base = "rv64i"; 214 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 215 216 interrupt-controller { 217 #interrupt-cells = <1>; 218 interrupt-controller; 219 compatible = "riscv,cpu-intc"; 220 }; 221 }; 222 }; 223... 224