1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 - $ref: extensions.yaml 29 30properties: 31 compatible: 32 oneOf: 33 - items: 34 - enum: 35 - andestech,ax45mp 36 - canaan,k210 37 - sifive,bullet0 38 - sifive,e5 39 - sifive,e7 40 - sifive,e71 41 - sifive,rocket0 42 - sifive,s7 43 - sifive,u5 44 - sifive,u54 45 - sifive,u7 46 - sifive,u74 47 - sifive,u74-mc 48 - thead,c906 49 - thead,c910 50 - thead,c920 51 - const: riscv 52 - items: 53 - enum: 54 - sifive,e51 55 - sifive,u54-mc 56 - const: sifive,rocket0 57 - const: riscv 58 - const: riscv # Simulator only 59 description: 60 Identifies that the hart uses the RISC-V instruction set 61 and identifies the type of the hart. 62 63 mmu-type: 64 description: 65 Identifies the MMU address translation mode used on this 66 hart. These values originate from the RISC-V Privileged 67 Specification document, available from 68 https://riscv.org/specifications/ 69 $ref: /schemas/types.yaml#/definitions/string 70 enum: 71 - riscv,sv32 72 - riscv,sv39 73 - riscv,sv48 74 - riscv,sv57 75 - riscv,none 76 77 riscv,cbom-block-size: 78 $ref: /schemas/types.yaml#/definitions/uint32 79 description: 80 The blocksize in bytes for the Zicbom cache operations. 81 82 riscv,cboz-block-size: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 description: 85 The blocksize in bytes for the Zicboz cache operations. 86 87 # RISC-V has multiple properties for cache op block sizes as the sizes 88 # differ between individual CBO extensions 89 cache-op-block-size: false 90 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 91 timebase-frequency: false 92 93 interrupt-controller: 94 type: object 95 additionalProperties: false 96 description: Describes the CPU's local interrupt controller 97 98 properties: 99 '#interrupt-cells': 100 const: 1 101 102 compatible: 103 const: riscv,cpu-intc 104 105 interrupt-controller: true 106 107 required: 108 - '#interrupt-cells' 109 - compatible 110 - interrupt-controller 111 112 cpu-idle-states: 113 $ref: /schemas/types.yaml#/definitions/phandle-array 114 items: 115 maxItems: 1 116 description: | 117 List of phandles to idle state nodes supported 118 by this hart (see ./idle-states.yaml). 119 120 capacity-dmips-mhz: 121 description: 122 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 123 DMIPS/MHz, relative to highest capacity-dmips-mhz 124 in the system. 125 126anyOf: 127 - required: 128 - riscv,isa 129 - required: 130 - riscv,isa-base 131 132dependencies: 133 riscv,isa-base: [ "riscv,isa-extensions" ] 134 riscv,isa-extensions: [ "riscv,isa-base" ] 135 136required: 137 - interrupt-controller 138 139unevaluatedProperties: false 140 141examples: 142 - | 143 // Example 1: SiFive Freedom U540G Development Kit 144 cpus { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 timebase-frequency = <1000000>; 148 cpu@0 { 149 clock-frequency = <0>; 150 compatible = "sifive,rocket0", "riscv"; 151 device_type = "cpu"; 152 i-cache-block-size = <64>; 153 i-cache-sets = <128>; 154 i-cache-size = <16384>; 155 reg = <0>; 156 riscv,isa-base = "rv64i"; 157 riscv,isa-extensions = "i", "m", "a", "c"; 158 159 cpu_intc0: interrupt-controller { 160 #interrupt-cells = <1>; 161 compatible = "riscv,cpu-intc"; 162 interrupt-controller; 163 }; 164 }; 165 cpu@1 { 166 clock-frequency = <0>; 167 compatible = "sifive,rocket0", "riscv"; 168 d-cache-block-size = <64>; 169 d-cache-sets = <64>; 170 d-cache-size = <32768>; 171 d-tlb-sets = <1>; 172 d-tlb-size = <32>; 173 device_type = "cpu"; 174 i-cache-block-size = <64>; 175 i-cache-sets = <64>; 176 i-cache-size = <32768>; 177 i-tlb-sets = <1>; 178 i-tlb-size = <32>; 179 mmu-type = "riscv,sv39"; 180 reg = <1>; 181 tlb-split; 182 riscv,isa-base = "rv64i"; 183 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 184 185 cpu_intc1: interrupt-controller { 186 #interrupt-cells = <1>; 187 compatible = "riscv,cpu-intc"; 188 interrupt-controller; 189 }; 190 }; 191 }; 192 193 - | 194 // Example 2: Spike ISA Simulator with 1 Hart 195 cpus { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 cpu@0 { 199 device_type = "cpu"; 200 reg = <0>; 201 compatible = "riscv"; 202 mmu-type = "riscv,sv48"; 203 riscv,isa-base = "rv64i"; 204 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 205 206 interrupt-controller { 207 #interrupt-cells = <1>; 208 interrupt-controller; 209 compatible = "riscv,cpu-intc"; 210 }; 211 }; 212 }; 213... 214