1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 - $ref: extensions.yaml 29 - if: 30 not: 31 properties: 32 compatible: 33 contains: 34 enum: 35 - thead,c906 36 - thead,c910 37 - thead,c920 38 then: 39 properties: 40 thead,vlenb: false 41 42properties: 43 compatible: 44 oneOf: 45 - items: 46 - enum: 47 - amd,mbv32 48 - andestech,ax45mp 49 - canaan,k210 50 - sifive,bullet0 51 - sifive,e5 52 - sifive,e7 53 - sifive,e71 54 - sifive,rocket0 55 - sifive,s7 56 - sifive,u5 57 - sifive,u54 58 - sifive,u7 59 - sifive,u74 60 - sifive,u74-mc 61 - thead,c906 62 - thead,c908 63 - thead,c910 64 - thead,c920 65 - const: riscv 66 - items: 67 - enum: 68 - sifive,e51 69 - sifive,u54-mc 70 - const: sifive,rocket0 71 - const: riscv 72 - const: riscv # Simulator only 73 description: 74 Identifies that the hart uses the RISC-V instruction set 75 and identifies the type of the hart. 76 77 mmu-type: 78 description: 79 Identifies the largest MMU address translation mode supported by 80 this hart. These values originate from the RISC-V Privileged 81 Specification document, available from 82 https://riscv.org/specifications/ 83 $ref: /schemas/types.yaml#/definitions/string 84 enum: 85 - riscv,sv32 86 - riscv,sv39 87 - riscv,sv48 88 - riscv,sv57 89 - riscv,none 90 91 reg: 92 description: 93 The hart ID of this CPU node. 94 95 riscv,cbom-block-size: 96 $ref: /schemas/types.yaml#/definitions/uint32 97 description: 98 The blocksize in bytes for the Zicbom cache operations. 99 100 riscv,cbop-block-size: 101 $ref: /schemas/types.yaml#/definitions/uint32 102 description: 103 The blocksize in bytes for the Zicbop cache operations. 104 105 riscv,cboz-block-size: 106 $ref: /schemas/types.yaml#/definitions/uint32 107 description: 108 The blocksize in bytes for the Zicboz cache operations. 109 110 thead,vlenb: 111 $ref: /schemas/types.yaml#/definitions/uint32 112 description: 113 VLEN/8, the vector register length in bytes. This property is required on 114 thead systems where the vector register length is not identical on all harts, or 115 the vlenb CSR is not available. 116 117 # RISC-V has multiple properties for cache op block sizes as the sizes 118 # differ between individual CBO extensions 119 cache-op-block-size: false 120 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 121 timebase-frequency: false 122 123 interrupt-controller: 124 type: object 125 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# 126 127 cpu-idle-states: 128 $ref: /schemas/types.yaml#/definitions/phandle-array 129 items: 130 maxItems: 1 131 description: | 132 List of phandles to idle state nodes supported 133 by this hart (see ./idle-states.yaml). 134 135 capacity-dmips-mhz: 136 description: 137 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 138 DMIPS/MHz, relative to highest capacity-dmips-mhz 139 in the system. 140 141anyOf: 142 - required: 143 - riscv,isa 144 - required: 145 - riscv,isa-base 146 147dependencies: 148 riscv,isa-base: [ "riscv,isa-extensions" ] 149 riscv,isa-extensions: [ "riscv,isa-base" ] 150 151required: 152 - interrupt-controller 153 154unevaluatedProperties: false 155 156examples: 157 - | 158 // Example 1: SiFive Freedom U540G Development Kit 159 cpus { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 timebase-frequency = <1000000>; 163 cpu@0 { 164 clock-frequency = <0>; 165 compatible = "sifive,rocket0", "riscv"; 166 device_type = "cpu"; 167 i-cache-block-size = <64>; 168 i-cache-sets = <128>; 169 i-cache-size = <16384>; 170 reg = <0>; 171 riscv,isa-base = "rv64i"; 172 riscv,isa-extensions = "i", "m", "a", "c"; 173 174 cpu_intc0: interrupt-controller { 175 #interrupt-cells = <1>; 176 compatible = "riscv,cpu-intc"; 177 interrupt-controller; 178 }; 179 }; 180 cpu@1 { 181 clock-frequency = <0>; 182 compatible = "sifive,rocket0", "riscv"; 183 d-cache-block-size = <64>; 184 d-cache-sets = <64>; 185 d-cache-size = <32768>; 186 d-tlb-sets = <1>; 187 d-tlb-size = <32>; 188 device_type = "cpu"; 189 i-cache-block-size = <64>; 190 i-cache-sets = <64>; 191 i-cache-size = <32768>; 192 i-tlb-sets = <1>; 193 i-tlb-size = <32>; 194 mmu-type = "riscv,sv39"; 195 reg = <1>; 196 tlb-split; 197 riscv,isa-base = "rv64i"; 198 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 199 200 cpu_intc1: interrupt-controller { 201 #interrupt-cells = <1>; 202 compatible = "riscv,cpu-intc"; 203 interrupt-controller; 204 }; 205 }; 206 }; 207 208 - | 209 // Example 2: Spike ISA Simulator with 1 Hart 210 cpus { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 cpu@0 { 214 device_type = "cpu"; 215 reg = <0>; 216 compatible = "riscv"; 217 mmu-type = "riscv,sv48"; 218 riscv,isa-base = "rv64i"; 219 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 220 221 interrupt-controller { 222 #interrupt-cells = <1>; 223 interrupt-controller; 224 compatible = "riscv,cpu-intc"; 225 }; 226 }; 227 }; 228... 229