xref: /linux/Documentation/devicetree/bindings/riscv/cpus.yaml (revision 5acac83bf2e42f51ab9fd315d657798754bf0bb8) 
1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/riscv/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V bindings for 'cpus' DT nodes
8
9maintainers:
10  - Paul Walmsley <paul.walmsley@sifive.com>
11  - Palmer Dabbelt <palmer@sifive.com>
12
13description: |
14  This document uses some terminology common to the RISC-V community
15  that is not widely used, the definitions of which are listed here:
16
17  hart: A hardware execution context, which contains all the state
18  mandated by the RISC-V ISA: a PC and some registers.  This
19  terminology is designed to disambiguate software's view of execution
20  contexts from any particular microarchitectural implementation
21  strategy.  For example, an Intel laptop containing one socket with
22  two cores, each of which has two hyperthreads, could be described as
23  having four harts.
24
25properties:
26  compatible:
27    oneOf:
28      - items:
29          - enum:
30              - sifive,rocket0
31              - sifive,bullet0
32              - sifive,e5
33              - sifive,e7
34              - sifive,e51
35              - sifive,e71
36              - sifive,u54-mc
37              - sifive,u74-mc
38              - sifive,u54
39              - sifive,u74
40              - sifive,u5
41              - sifive,u7
42              - canaan,k210
43          - const: riscv
44      - const: riscv    # Simulator only
45    description:
46      Identifies that the hart uses the RISC-V instruction set
47      and identifies the type of the hart.
48
49  mmu-type:
50    description:
51      Identifies the MMU address translation mode used on this
52      hart.  These values originate from the RISC-V Privileged
53      Specification document, available from
54      https://riscv.org/specifications/
55    $ref: "/schemas/types.yaml#/definitions/string"
56    enum:
57      - riscv,sv32
58      - riscv,sv39
59      - riscv,sv48
60      - riscv,none
61
62  riscv,isa:
63    description:
64      Identifies the specific RISC-V instruction set architecture
65      supported by the hart.  These are documented in the RISC-V
66      User-Level ISA document, available from
67      https://riscv.org/specifications/
68
69      While the isa strings in ISA specification are case
70      insensitive, letters in the riscv,isa string must be all
71      lowercase to simplify parsing.
72    $ref: "/schemas/types.yaml#/definitions/string"
73    enum:
74      - rv64imac
75      - rv64imafdc
76
77  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
78  timebase-frequency: false
79
80  interrupt-controller:
81    type: object
82    description: Describes the CPU's local interrupt controller
83
84    properties:
85      '#interrupt-cells':
86        const: 1
87
88      compatible:
89        const: riscv,cpu-intc
90
91      interrupt-controller: true
92
93    required:
94      - '#interrupt-cells'
95      - compatible
96      - interrupt-controller
97
98required:
99  - riscv,isa
100  - interrupt-controller
101
102additionalProperties: true
103
104examples:
105  - |
106    // Example 1: SiFive Freedom U540G Development Kit
107    cpus {
108        #address-cells = <1>;
109        #size-cells = <0>;
110        timebase-frequency = <1000000>;
111        cpu@0 {
112                clock-frequency = <0>;
113                compatible = "sifive,rocket0", "riscv";
114                device_type = "cpu";
115                i-cache-block-size = <64>;
116                i-cache-sets = <128>;
117                i-cache-size = <16384>;
118                reg = <0>;
119                riscv,isa = "rv64imac";
120                cpu_intc0: interrupt-controller {
121                        #interrupt-cells = <1>;
122                        compatible = "riscv,cpu-intc";
123                        interrupt-controller;
124                };
125        };
126        cpu@1 {
127                clock-frequency = <0>;
128                compatible = "sifive,rocket0", "riscv";
129                d-cache-block-size = <64>;
130                d-cache-sets = <64>;
131                d-cache-size = <32768>;
132                d-tlb-sets = <1>;
133                d-tlb-size = <32>;
134                device_type = "cpu";
135                i-cache-block-size = <64>;
136                i-cache-sets = <64>;
137                i-cache-size = <32768>;
138                i-tlb-sets = <1>;
139                i-tlb-size = <32>;
140                mmu-type = "riscv,sv39";
141                reg = <1>;
142                riscv,isa = "rv64imafdc";
143                tlb-split;
144                cpu_intc1: interrupt-controller {
145                        #interrupt-cells = <1>;
146                        compatible = "riscv,cpu-intc";
147                        interrupt-controller;
148                };
149        };
150    };
151
152  - |
153    // Example 2: Spike ISA Simulator with 1 Hart
154    cpus {
155        #address-cells = <1>;
156        #size-cells = <0>;
157        cpu@0 {
158                device_type = "cpu";
159                reg = <0>;
160                compatible = "riscv";
161                riscv,isa = "rv64imafdc";
162                mmu-type = "riscv,sv48";
163                interrupt-controller {
164                        #interrupt-cells = <1>;
165                        interrupt-controller;
166                        compatible = "riscv,cpu-intc";
167                };
168        };
169    };
170...
171