1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 - $ref: extensions.yaml 29 - if: 30 not: 31 properties: 32 compatible: 33 contains: 34 enum: 35 - thead,c906 36 - thead,c910 37 - thead,c920 38 then: 39 properties: 40 thead,vlenb: false 41 42properties: 43 compatible: 44 oneOf: 45 - items: 46 - enum: 47 - amd,mbv32 48 - amd,mbv64 49 - andestech,ax45mp 50 - canaan,k210 51 - sifive,bullet0 52 - sifive,e5 53 - sifive,e7 54 - sifive,e71 55 - sifive,p550 56 - sifive,rocket0 57 - sifive,s7 58 - sifive,u5 59 - sifive,u54 60 - sifive,u7 61 - sifive,u74 62 - sifive,u74-mc 63 - spacemit,x60 64 - thead,c906 65 - thead,c908 66 - thead,c910 67 - thead,c920 68 - const: riscv 69 - items: 70 - enum: 71 - sifive,e51 72 - sifive,u54-mc 73 - const: sifive,rocket0 74 - const: riscv 75 - const: riscv # Simulator only 76 description: 77 Identifies that the hart uses the RISC-V instruction set 78 and identifies the type of the hart. 79 80 mmu-type: 81 description: 82 Identifies the largest MMU address translation mode supported by 83 this hart. These values originate from the RISC-V Privileged 84 Specification document, available from 85 https://riscv.org/specifications/ 86 $ref: /schemas/types.yaml#/definitions/string 87 enum: 88 - riscv,sv32 89 - riscv,sv39 90 - riscv,sv48 91 - riscv,sv57 92 - riscv,none 93 94 reg: 95 description: 96 The hart ID of this CPU node. 97 98 riscv,cbom-block-size: 99 $ref: /schemas/types.yaml#/definitions/uint32 100 description: 101 The blocksize in bytes for the Zicbom cache operations. 102 103 riscv,cbop-block-size: 104 $ref: /schemas/types.yaml#/definitions/uint32 105 description: 106 The blocksize in bytes for the Zicbop cache operations. 107 108 riscv,cboz-block-size: 109 $ref: /schemas/types.yaml#/definitions/uint32 110 description: 111 The blocksize in bytes for the Zicboz cache operations. 112 113 thead,vlenb: 114 $ref: /schemas/types.yaml#/definitions/uint32 115 description: 116 VLEN/8, the vector register length in bytes. This property is required on 117 thead systems where the vector register length is not identical on all harts, or 118 the vlenb CSR is not available. 119 120 # RISC-V has multiple properties for cache op block sizes as the sizes 121 # differ between individual CBO extensions 122 cache-op-block-size: false 123 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 124 timebase-frequency: false 125 126 interrupt-controller: 127 type: object 128 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# 129 130 cpu-idle-states: 131 $ref: /schemas/types.yaml#/definitions/phandle-array 132 items: 133 maxItems: 1 134 description: | 135 List of phandles to idle state nodes supported 136 by this hart (see ./idle-states.yaml). 137 138 capacity-dmips-mhz: 139 description: 140 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 141 DMIPS/MHz, relative to highest capacity-dmips-mhz 142 in the system. 143 144anyOf: 145 - required: 146 - riscv,isa 147 - required: 148 - riscv,isa-base 149 150dependencies: 151 riscv,isa-base: [ "riscv,isa-extensions" ] 152 riscv,isa-extensions: [ "riscv,isa-base" ] 153 154required: 155 - interrupt-controller 156 157unevaluatedProperties: false 158 159examples: 160 - | 161 // Example 1: SiFive Freedom U540G Development Kit 162 cpus { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 timebase-frequency = <1000000>; 166 cpu@0 { 167 clock-frequency = <0>; 168 compatible = "sifive,rocket0", "riscv"; 169 device_type = "cpu"; 170 i-cache-block-size = <64>; 171 i-cache-sets = <128>; 172 i-cache-size = <16384>; 173 reg = <0>; 174 riscv,isa-base = "rv64i"; 175 riscv,isa-extensions = "i", "m", "a", "c"; 176 177 cpu_intc0: interrupt-controller { 178 #interrupt-cells = <1>; 179 compatible = "riscv,cpu-intc"; 180 interrupt-controller; 181 }; 182 }; 183 cpu@1 { 184 clock-frequency = <0>; 185 compatible = "sifive,rocket0", "riscv"; 186 d-cache-block-size = <64>; 187 d-cache-sets = <64>; 188 d-cache-size = <32768>; 189 d-tlb-sets = <1>; 190 d-tlb-size = <32>; 191 device_type = "cpu"; 192 i-cache-block-size = <64>; 193 i-cache-sets = <64>; 194 i-cache-size = <32768>; 195 i-tlb-sets = <1>; 196 i-tlb-size = <32>; 197 mmu-type = "riscv,sv39"; 198 reg = <1>; 199 tlb-split; 200 riscv,isa-base = "rv64i"; 201 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 202 203 cpu_intc1: interrupt-controller { 204 #interrupt-cells = <1>; 205 compatible = "riscv,cpu-intc"; 206 interrupt-controller; 207 }; 208 }; 209 }; 210 211 - | 212 // Example 2: Spike ISA Simulator with 1 Hart 213 cpus { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 cpu@0 { 217 device_type = "cpu"; 218 reg = <0>; 219 compatible = "riscv"; 220 mmu-type = "riscv,sv48"; 221 riscv,isa-base = "rv64i"; 222 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 223 224 interrupt-controller { 225 #interrupt-cells = <1>; 226 interrupt-controller; 227 compatible = "riscv,cpu-intc"; 228 }; 229 }; 230 }; 231... 232