1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26properties: 27 compatible: 28 oneOf: 29 - items: 30 - enum: 31 - andestech,ax45mp 32 - canaan,k210 33 - sifive,bullet0 34 - sifive,e5 35 - sifive,e7 36 - sifive,e71 37 - sifive,rocket0 38 - sifive,s7 39 - sifive,u5 40 - sifive,u54 41 - sifive,u7 42 - sifive,u74 43 - sifive,u74-mc 44 - thead,c906 45 - thead,c910 46 - const: riscv 47 - items: 48 - enum: 49 - sifive,e51 50 - sifive,u54-mc 51 - const: sifive,rocket0 52 - const: riscv 53 - const: riscv # Simulator only 54 description: 55 Identifies that the hart uses the RISC-V instruction set 56 and identifies the type of the hart. 57 58 mmu-type: 59 description: 60 Identifies the MMU address translation mode used on this 61 hart. These values originate from the RISC-V Privileged 62 Specification document, available from 63 https://riscv.org/specifications/ 64 $ref: "/schemas/types.yaml#/definitions/string" 65 enum: 66 - riscv,sv32 67 - riscv,sv39 68 - riscv,sv48 69 - riscv,sv57 70 - riscv,none 71 72 riscv,cbom-block-size: 73 $ref: /schemas/types.yaml#/definitions/uint32 74 description: 75 The blocksize in bytes for the Zicbom cache operations. 76 77 riscv,cboz-block-size: 78 $ref: /schemas/types.yaml#/definitions/uint32 79 description: 80 The blocksize in bytes for the Zicboz cache operations. 81 82 riscv,isa: 83 description: 84 Identifies the specific RISC-V instruction set architecture 85 supported by the hart. These are documented in the RISC-V 86 User-Level ISA document, available from 87 https://riscv.org/specifications/ 88 89 Due to revisions of the ISA specification, some deviations 90 have arisen over time. 91 Notably, riscv,isa was defined prior to the creation of the 92 Zicsr and Zifencei extensions and thus "i" implies 93 "zicsr_zifencei". 94 95 While the isa strings in ISA specification are case 96 insensitive, letters in the riscv,isa string must be all 97 lowercase to simplify parsing. 98 $ref: "/schemas/types.yaml#/definitions/string" 99 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ 100 101 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 102 timebase-frequency: false 103 104 interrupt-controller: 105 type: object 106 description: Describes the CPU's local interrupt controller 107 108 properties: 109 '#interrupt-cells': 110 const: 1 111 112 compatible: 113 const: riscv,cpu-intc 114 115 interrupt-controller: true 116 117 required: 118 - '#interrupt-cells' 119 - compatible 120 - interrupt-controller 121 122 cpu-idle-states: 123 $ref: '/schemas/types.yaml#/definitions/phandle-array' 124 items: 125 maxItems: 1 126 description: | 127 List of phandles to idle state nodes supported 128 by this hart (see ./idle-states.yaml). 129 130 capacity-dmips-mhz: 131 description: 132 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 133 DMIPS/MHz, relative to highest capacity-dmips-mhz 134 in the system. 135 136required: 137 - riscv,isa 138 - interrupt-controller 139 140additionalProperties: true 141 142examples: 143 - | 144 // Example 1: SiFive Freedom U540G Development Kit 145 cpus { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 timebase-frequency = <1000000>; 149 cpu@0 { 150 clock-frequency = <0>; 151 compatible = "sifive,rocket0", "riscv"; 152 device_type = "cpu"; 153 i-cache-block-size = <64>; 154 i-cache-sets = <128>; 155 i-cache-size = <16384>; 156 reg = <0>; 157 riscv,isa = "rv64imac"; 158 cpu_intc0: interrupt-controller { 159 #interrupt-cells = <1>; 160 compatible = "riscv,cpu-intc"; 161 interrupt-controller; 162 }; 163 }; 164 cpu@1 { 165 clock-frequency = <0>; 166 compatible = "sifive,rocket0", "riscv"; 167 d-cache-block-size = <64>; 168 d-cache-sets = <64>; 169 d-cache-size = <32768>; 170 d-tlb-sets = <1>; 171 d-tlb-size = <32>; 172 device_type = "cpu"; 173 i-cache-block-size = <64>; 174 i-cache-sets = <64>; 175 i-cache-size = <32768>; 176 i-tlb-sets = <1>; 177 i-tlb-size = <32>; 178 mmu-type = "riscv,sv39"; 179 reg = <1>; 180 riscv,isa = "rv64imafdc"; 181 tlb-split; 182 cpu_intc1: interrupt-controller { 183 #interrupt-cells = <1>; 184 compatible = "riscv,cpu-intc"; 185 interrupt-controller; 186 }; 187 }; 188 }; 189 190 - | 191 // Example 2: Spike ISA Simulator with 1 Hart 192 cpus { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 cpu@0 { 196 device_type = "cpu"; 197 reg = <0>; 198 compatible = "riscv"; 199 riscv,isa = "rv64imafdc"; 200 mmu-type = "riscv,sv48"; 201 interrupt-controller { 202 #interrupt-cells = <1>; 203 interrupt-controller; 204 compatible = "riscv,cpu-intc"; 205 }; 206 }; 207 }; 208... 209