1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 - $ref: extensions.yaml 29 - if: 30 not: 31 properties: 32 compatible: 33 contains: 34 enum: 35 - thead,c906 36 - thead,c910 37 - thead,c920 38 then: 39 properties: 40 thead,vlenb: false 41 42properties: 43 compatible: 44 oneOf: 45 - items: 46 - enum: 47 - amd,mbv32 48 - amd,mbv64 49 - andestech,ax45mp 50 - canaan,k210 51 - sifive,bullet0 52 - sifive,e5 53 - sifive,e7 54 - sifive,e71 55 - sifive,rocket0 56 - sifive,s7 57 - sifive,u5 58 - sifive,u54 59 - sifive,u7 60 - sifive,u74 61 - sifive,u74-mc 62 - spacemit,x60 63 - thead,c906 64 - thead,c908 65 - thead,c910 66 - thead,c920 67 - const: riscv 68 - items: 69 - enum: 70 - sifive,e51 71 - sifive,u54-mc 72 - const: sifive,rocket0 73 - const: riscv 74 - const: riscv # Simulator only 75 description: 76 Identifies that the hart uses the RISC-V instruction set 77 and identifies the type of the hart. 78 79 mmu-type: 80 description: 81 Identifies the largest MMU address translation mode supported by 82 this hart. These values originate from the RISC-V Privileged 83 Specification document, available from 84 https://riscv.org/specifications/ 85 $ref: /schemas/types.yaml#/definitions/string 86 enum: 87 - riscv,sv32 88 - riscv,sv39 89 - riscv,sv48 90 - riscv,sv57 91 - riscv,none 92 93 reg: 94 description: 95 The hart ID of this CPU node. 96 97 riscv,cbom-block-size: 98 $ref: /schemas/types.yaml#/definitions/uint32 99 description: 100 The blocksize in bytes for the Zicbom cache operations. 101 102 riscv,cbop-block-size: 103 $ref: /schemas/types.yaml#/definitions/uint32 104 description: 105 The blocksize in bytes for the Zicbop cache operations. 106 107 riscv,cboz-block-size: 108 $ref: /schemas/types.yaml#/definitions/uint32 109 description: 110 The blocksize in bytes for the Zicboz cache operations. 111 112 thead,vlenb: 113 $ref: /schemas/types.yaml#/definitions/uint32 114 description: 115 VLEN/8, the vector register length in bytes. This property is required on 116 thead systems where the vector register length is not identical on all harts, or 117 the vlenb CSR is not available. 118 119 # RISC-V has multiple properties for cache op block sizes as the sizes 120 # differ between individual CBO extensions 121 cache-op-block-size: false 122 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 123 timebase-frequency: false 124 125 interrupt-controller: 126 type: object 127 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# 128 129 cpu-idle-states: 130 $ref: /schemas/types.yaml#/definitions/phandle-array 131 items: 132 maxItems: 1 133 description: | 134 List of phandles to idle state nodes supported 135 by this hart (see ./idle-states.yaml). 136 137 capacity-dmips-mhz: 138 description: 139 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 140 DMIPS/MHz, relative to highest capacity-dmips-mhz 141 in the system. 142 143anyOf: 144 - required: 145 - riscv,isa 146 - required: 147 - riscv,isa-base 148 149dependencies: 150 riscv,isa-base: [ "riscv,isa-extensions" ] 151 riscv,isa-extensions: [ "riscv,isa-base" ] 152 153required: 154 - interrupt-controller 155 156unevaluatedProperties: false 157 158examples: 159 - | 160 // Example 1: SiFive Freedom U540G Development Kit 161 cpus { 162 #address-cells = <1>; 163 #size-cells = <0>; 164 timebase-frequency = <1000000>; 165 cpu@0 { 166 clock-frequency = <0>; 167 compatible = "sifive,rocket0", "riscv"; 168 device_type = "cpu"; 169 i-cache-block-size = <64>; 170 i-cache-sets = <128>; 171 i-cache-size = <16384>; 172 reg = <0>; 173 riscv,isa-base = "rv64i"; 174 riscv,isa-extensions = "i", "m", "a", "c"; 175 176 cpu_intc0: interrupt-controller { 177 #interrupt-cells = <1>; 178 compatible = "riscv,cpu-intc"; 179 interrupt-controller; 180 }; 181 }; 182 cpu@1 { 183 clock-frequency = <0>; 184 compatible = "sifive,rocket0", "riscv"; 185 d-cache-block-size = <64>; 186 d-cache-sets = <64>; 187 d-cache-size = <32768>; 188 d-tlb-sets = <1>; 189 d-tlb-size = <32>; 190 device_type = "cpu"; 191 i-cache-block-size = <64>; 192 i-cache-sets = <64>; 193 i-cache-size = <32768>; 194 i-tlb-sets = <1>; 195 i-tlb-size = <32>; 196 mmu-type = "riscv,sv39"; 197 reg = <1>; 198 tlb-split; 199 riscv,isa-base = "rv64i"; 200 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 201 202 cpu_intc1: interrupt-controller { 203 #interrupt-cells = <1>; 204 compatible = "riscv,cpu-intc"; 205 interrupt-controller; 206 }; 207 }; 208 }; 209 210 - | 211 // Example 2: Spike ISA Simulator with 1 Hart 212 cpus { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 cpu@0 { 216 device_type = "cpu"; 217 reg = <0>; 218 compatible = "riscv"; 219 mmu-type = "riscv,sv48"; 220 riscv,isa-base = "rv64i"; 221 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 222 223 interrupt-controller { 224 #interrupt-cells = <1>; 225 interrupt-controller; 226 compatible = "riscv,cpu-intc"; 227 }; 228 }; 229 }; 230... 231