1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 - $ref: extensions.yaml 29 - if: 30 not: 31 properties: 32 compatible: 33 contains: 34 enum: 35 - thead,c906 36 - thead,c910 37 - thead,c920 38 then: 39 properties: 40 thead,vlenb: false 41 42properties: 43 compatible: 44 oneOf: 45 - items: 46 - enum: 47 - amd,mbv32 48 - amd,mbv64 49 - andestech,ax45mp 50 - canaan,k210 51 - nuclei,ux900 52 - sifive,bullet0 53 - sifive,e5 54 - sifive,e7 55 - sifive,e71 56 - sifive,p550 57 - sifive,rocket0 58 - sifive,s7 59 - sifive,u5 60 - sifive,u54 61 - sifive,u7 62 - sifive,u74 63 - sifive,u74-mc 64 - spacemit,x100 65 - spacemit,x60 66 - thead,c906 67 - thead,c908 68 - thead,c910 69 - thead,c920 70 - const: riscv 71 - items: 72 - enum: 73 - sifive,e51 74 - sifive,u54-mc 75 - sifive,x280 76 - const: sifive,rocket0 77 - const: riscv 78 - const: riscv # Simulator only 79 description: 80 Identifies that the hart uses the RISC-V instruction set 81 and identifies the type of the hart. 82 83 mmu-type: 84 description: 85 Identifies the largest MMU address translation mode supported by 86 this hart. These values originate from the RISC-V Privileged 87 Specification document, available from 88 https://riscv.org/specifications/ 89 $ref: /schemas/types.yaml#/definitions/string 90 enum: 91 - riscv,sv32 92 - riscv,sv39 93 - riscv,sv48 94 - riscv,sv57 95 - riscv,none 96 97 reg: 98 description: 99 The hart ID of this CPU node. 100 101 riscv,cbom-block-size: 102 $ref: /schemas/types.yaml#/definitions/uint32 103 description: 104 The blocksize in bytes for the Zicbom cache operations. 105 106 riscv,cbop-block-size: 107 $ref: /schemas/types.yaml#/definitions/uint32 108 description: 109 The blocksize in bytes for the Zicbop cache operations. 110 111 riscv,cboz-block-size: 112 $ref: /schemas/types.yaml#/definitions/uint32 113 description: 114 The blocksize in bytes for the Zicboz cache operations. 115 116 thead,vlenb: 117 $ref: /schemas/types.yaml#/definitions/uint32 118 description: 119 VLEN/8, the vector register length in bytes. This property is required on 120 thead systems where the vector register length is not identical on all harts, or 121 the vlenb CSR is not available. 122 123 # RISC-V has multiple properties for cache op block sizes as the sizes 124 # differ between individual CBO extensions 125 cache-op-block-size: false 126 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 127 timebase-frequency: false 128 129 interrupt-controller: 130 type: object 131 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# 132 133 cpu-idle-states: 134 $ref: /schemas/types.yaml#/definitions/phandle-array 135 items: 136 maxItems: 1 137 description: | 138 List of phandles to idle state nodes supported 139 by this hart (see ./idle-states.yaml). 140 141 capacity-dmips-mhz: 142 description: 143 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 144 DMIPS/MHz, relative to highest capacity-dmips-mhz 145 in the system. 146 147anyOf: 148 - required: 149 - riscv,isa 150 - required: 151 - riscv,isa-base 152 153dependencies: 154 riscv,isa-base: [ "riscv,isa-extensions" ] 155 riscv,isa-extensions: [ "riscv,isa-base" ] 156 157required: 158 - interrupt-controller 159 160unevaluatedProperties: false 161 162examples: 163 - | 164 // Example 1: SiFive Freedom U540G Development Kit 165 cpus { 166 #address-cells = <1>; 167 #size-cells = <0>; 168 timebase-frequency = <1000000>; 169 cpu@0 { 170 clock-frequency = <0>; 171 compatible = "sifive,rocket0", "riscv"; 172 device_type = "cpu"; 173 i-cache-block-size = <64>; 174 i-cache-sets = <128>; 175 i-cache-size = <16384>; 176 reg = <0>; 177 riscv,isa-base = "rv64i"; 178 riscv,isa-extensions = "i", "m", "a", "c"; 179 180 cpu_intc0: interrupt-controller { 181 #interrupt-cells = <1>; 182 compatible = "riscv,cpu-intc"; 183 interrupt-controller; 184 }; 185 }; 186 cpu@1 { 187 clock-frequency = <0>; 188 compatible = "sifive,rocket0", "riscv"; 189 d-cache-block-size = <64>; 190 d-cache-sets = <64>; 191 d-cache-size = <32768>; 192 d-tlb-sets = <1>; 193 d-tlb-size = <32>; 194 device_type = "cpu"; 195 i-cache-block-size = <64>; 196 i-cache-sets = <64>; 197 i-cache-size = <32768>; 198 i-tlb-sets = <1>; 199 i-tlb-size = <32>; 200 mmu-type = "riscv,sv39"; 201 reg = <1>; 202 tlb-split; 203 riscv,isa-base = "rv64i"; 204 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 205 206 cpu_intc1: interrupt-controller { 207 #interrupt-cells = <1>; 208 compatible = "riscv,cpu-intc"; 209 interrupt-controller; 210 }; 211 }; 212 }; 213 214 - | 215 // Example 2: Spike ISA Simulator with 1 Hart 216 cpus { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 cpu@0 { 220 device_type = "cpu"; 221 reg = <0>; 222 compatible = "riscv"; 223 mmu-type = "riscv,sv48"; 224 riscv,isa-base = "rv64i"; 225 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 226 227 interrupt-controller { 228 #interrupt-cells = <1>; 229 interrupt-controller; 230 compatible = "riscv,cpu-intc"; 231 }; 232 }; 233 }; 234... 235