1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 - $ref: extensions.yaml 29 30properties: 31 compatible: 32 oneOf: 33 - items: 34 - enum: 35 - amd,mbv32 36 - andestech,ax45mp 37 - canaan,k210 38 - sifive,bullet0 39 - sifive,e5 40 - sifive,e7 41 - sifive,e71 42 - sifive,rocket0 43 - sifive,s7 44 - sifive,u5 45 - sifive,u54 46 - sifive,u7 47 - sifive,u74 48 - sifive,u74-mc 49 - thead,c906 50 - thead,c910 51 - thead,c920 52 - const: riscv 53 - items: 54 - enum: 55 - sifive,e51 56 - sifive,u54-mc 57 - const: sifive,rocket0 58 - const: riscv 59 - const: riscv # Simulator only 60 description: 61 Identifies that the hart uses the RISC-V instruction set 62 and identifies the type of the hart. 63 64 mmu-type: 65 description: 66 Identifies the largest MMU address translation mode supported by 67 this hart. These values originate from the RISC-V Privileged 68 Specification document, available from 69 https://riscv.org/specifications/ 70 $ref: /schemas/types.yaml#/definitions/string 71 enum: 72 - riscv,sv32 73 - riscv,sv39 74 - riscv,sv48 75 - riscv,sv57 76 - riscv,none 77 78 reg: 79 description: 80 The hart ID of this CPU node. 81 82 riscv,cbom-block-size: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 description: 85 The blocksize in bytes for the Zicbom cache operations. 86 87 riscv,cbop-block-size: 88 $ref: /schemas/types.yaml#/definitions/uint32 89 description: 90 The blocksize in bytes for the Zicbop cache operations. 91 92 riscv,cboz-block-size: 93 $ref: /schemas/types.yaml#/definitions/uint32 94 description: 95 The blocksize in bytes for the Zicboz cache operations. 96 97 # RISC-V has multiple properties for cache op block sizes as the sizes 98 # differ between individual CBO extensions 99 cache-op-block-size: false 100 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 101 timebase-frequency: false 102 103 interrupt-controller: 104 type: object 105 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# 106 107 cpu-idle-states: 108 $ref: /schemas/types.yaml#/definitions/phandle-array 109 items: 110 maxItems: 1 111 description: | 112 List of phandles to idle state nodes supported 113 by this hart (see ./idle-states.yaml). 114 115 capacity-dmips-mhz: 116 description: 117 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 118 DMIPS/MHz, relative to highest capacity-dmips-mhz 119 in the system. 120 121anyOf: 122 - required: 123 - riscv,isa 124 - required: 125 - riscv,isa-base 126 127dependencies: 128 riscv,isa-base: [ "riscv,isa-extensions" ] 129 riscv,isa-extensions: [ "riscv,isa-base" ] 130 131required: 132 - interrupt-controller 133 134unevaluatedProperties: false 135 136examples: 137 - | 138 // Example 1: SiFive Freedom U540G Development Kit 139 cpus { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 timebase-frequency = <1000000>; 143 cpu@0 { 144 clock-frequency = <0>; 145 compatible = "sifive,rocket0", "riscv"; 146 device_type = "cpu"; 147 i-cache-block-size = <64>; 148 i-cache-sets = <128>; 149 i-cache-size = <16384>; 150 reg = <0>; 151 riscv,isa-base = "rv64i"; 152 riscv,isa-extensions = "i", "m", "a", "c"; 153 154 cpu_intc0: interrupt-controller { 155 #interrupt-cells = <1>; 156 compatible = "riscv,cpu-intc"; 157 interrupt-controller; 158 }; 159 }; 160 cpu@1 { 161 clock-frequency = <0>; 162 compatible = "sifive,rocket0", "riscv"; 163 d-cache-block-size = <64>; 164 d-cache-sets = <64>; 165 d-cache-size = <32768>; 166 d-tlb-sets = <1>; 167 d-tlb-size = <32>; 168 device_type = "cpu"; 169 i-cache-block-size = <64>; 170 i-cache-sets = <64>; 171 i-cache-size = <32768>; 172 i-tlb-sets = <1>; 173 i-tlb-size = <32>; 174 mmu-type = "riscv,sv39"; 175 reg = <1>; 176 tlb-split; 177 riscv,isa-base = "rv64i"; 178 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 179 180 cpu_intc1: interrupt-controller { 181 #interrupt-cells = <1>; 182 compatible = "riscv,cpu-intc"; 183 interrupt-controller; 184 }; 185 }; 186 }; 187 188 - | 189 // Example 2: Spike ISA Simulator with 1 Hart 190 cpus { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 cpu@0 { 194 device_type = "cpu"; 195 reg = <0>; 196 compatible = "riscv"; 197 mmu-type = "riscv,sv48"; 198 riscv,isa-base = "rv64i"; 199 riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 200 201 interrupt-controller { 202 #interrupt-cells = <1>; 203 interrupt-controller; 204 compatible = "riscv,cpu-intc"; 205 }; 206 }; 207 }; 208... 209