1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V CPUs 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 This document uses some terminology common to the RISC-V community 16 that is not widely used, the definitions of which are listed here: 17 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This 20 terminology is designed to disambiguate software's view of execution 21 contexts from any particular microarchitectural implementation 22 strategy. For example, an Intel laptop containing one socket with 23 two cores, each of which has two hyperthreads, could be described as 24 having four harts. 25 26allOf: 27 - $ref: /schemas/cpu.yaml# 28 29properties: 30 compatible: 31 oneOf: 32 - items: 33 - enum: 34 - andestech,ax45mp 35 - canaan,k210 36 - sifive,bullet0 37 - sifive,e5 38 - sifive,e7 39 - sifive,e71 40 - sifive,rocket0 41 - sifive,s7 42 - sifive,u5 43 - sifive,u54 44 - sifive,u7 45 - sifive,u74 46 - sifive,u74-mc 47 - thead,c906 48 - thead,c910 49 - const: riscv 50 - items: 51 - enum: 52 - sifive,e51 53 - sifive,u54-mc 54 - const: sifive,rocket0 55 - const: riscv 56 - const: riscv # Simulator only 57 description: 58 Identifies that the hart uses the RISC-V instruction set 59 and identifies the type of the hart. 60 61 mmu-type: 62 description: 63 Identifies the MMU address translation mode used on this 64 hart. These values originate from the RISC-V Privileged 65 Specification document, available from 66 https://riscv.org/specifications/ 67 $ref: /schemas/types.yaml#/definitions/string 68 enum: 69 - riscv,sv32 70 - riscv,sv39 71 - riscv,sv48 72 - riscv,sv57 73 - riscv,none 74 75 riscv,cbom-block-size: 76 $ref: /schemas/types.yaml#/definitions/uint32 77 description: 78 The blocksize in bytes for the Zicbom cache operations. 79 80 riscv,cboz-block-size: 81 $ref: /schemas/types.yaml#/definitions/uint32 82 description: 83 The blocksize in bytes for the Zicboz cache operations. 84 85 riscv,isa: 86 description: 87 Identifies the specific RISC-V instruction set architecture 88 supported by the hart. These are documented in the RISC-V 89 User-Level ISA document, available from 90 https://riscv.org/specifications/ 91 92 Due to revisions of the ISA specification, some deviations 93 have arisen over time. 94 Notably, riscv,isa was defined prior to the creation of the 95 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 96 implies "zicntr_zicsr_zifencei_zihpm". 97 98 While the isa strings in ISA specification are case 99 insensitive, letters in the riscv,isa string must be all 100 lowercase. 101 $ref: /schemas/types.yaml#/definitions/string 102 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ 103 104 # RISC-V has multiple properties for cache op block sizes as the sizes 105 # differ between individual CBO extensions 106 cache-op-block-size: false 107 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 108 timebase-frequency: false 109 110 interrupt-controller: 111 type: object 112 description: Describes the CPU's local interrupt controller 113 114 properties: 115 '#interrupt-cells': 116 const: 1 117 118 compatible: 119 const: riscv,cpu-intc 120 121 interrupt-controller: true 122 123 required: 124 - '#interrupt-cells' 125 - compatible 126 - interrupt-controller 127 128 cpu-idle-states: 129 $ref: /schemas/types.yaml#/definitions/phandle-array 130 items: 131 maxItems: 1 132 description: | 133 List of phandles to idle state nodes supported 134 by this hart (see ./idle-states.yaml). 135 136 capacity-dmips-mhz: 137 description: 138 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 139 DMIPS/MHz, relative to highest capacity-dmips-mhz 140 in the system. 141 142required: 143 - riscv,isa 144 - interrupt-controller 145 146unevaluatedProperties: false 147 148examples: 149 - | 150 // Example 1: SiFive Freedom U540G Development Kit 151 cpus { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 timebase-frequency = <1000000>; 155 cpu@0 { 156 clock-frequency = <0>; 157 compatible = "sifive,rocket0", "riscv"; 158 device_type = "cpu"; 159 i-cache-block-size = <64>; 160 i-cache-sets = <128>; 161 i-cache-size = <16384>; 162 reg = <0>; 163 riscv,isa = "rv64imac"; 164 cpu_intc0: interrupt-controller { 165 #interrupt-cells = <1>; 166 compatible = "riscv,cpu-intc"; 167 interrupt-controller; 168 }; 169 }; 170 cpu@1 { 171 clock-frequency = <0>; 172 compatible = "sifive,rocket0", "riscv"; 173 d-cache-block-size = <64>; 174 d-cache-sets = <64>; 175 d-cache-size = <32768>; 176 d-tlb-sets = <1>; 177 d-tlb-size = <32>; 178 device_type = "cpu"; 179 i-cache-block-size = <64>; 180 i-cache-sets = <64>; 181 i-cache-size = <32768>; 182 i-tlb-sets = <1>; 183 i-tlb-size = <32>; 184 mmu-type = "riscv,sv39"; 185 reg = <1>; 186 riscv,isa = "rv64imafdc"; 187 tlb-split; 188 cpu_intc1: interrupt-controller { 189 #interrupt-cells = <1>; 190 compatible = "riscv,cpu-intc"; 191 interrupt-controller; 192 }; 193 }; 194 }; 195 196 - | 197 // Example 2: Spike ISA Simulator with 1 Hart 198 cpus { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 cpu@0 { 202 device_type = "cpu"; 203 reg = <0>; 204 compatible = "riscv"; 205 riscv,isa = "rv64imafdc"; 206 mmu-type = "riscv,sv48"; 207 interrupt-controller { 208 #interrupt-cells = <1>; 209 interrupt-controller; 210 compatible = "riscv,cpu-intc"; 211 }; 212 }; 213 }; 214... 215