xref: /linux/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.yaml (revision 02680c23d7b3febe45ea3d4f9818c2b2dc89020a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Hisilicon System Reset Controller
8
9maintainers:
10  - Wei Xu <xuwei5@hisilicon.com>
11
12description: |
13  Please also refer to reset.txt in this directory for common reset
14  controller binding usage.
15  The reset controller registers are part of the system-ctl block on
16  hi3660 and hi3670 SoCs.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - const: hisilicon,hi3660-reset
23      - items:
24          - const: hisilicon,hi3670-reset
25          - const: hisilicon,hi3660-reset
26
27  hisilicon,rst-syscon:
28    description: phandle of the reset's syscon.
29    $ref: /schemas/types.yaml#/definitions/phandle
30
31  '#reset-cells':
32    description: |
33      Specifies the number of cells needed to encode a reset source.
34      Cell #1 : offset of the reset assert control register from the syscon
35                register base
36                offset + 4: deassert control register
37                offset + 8: status control register
38      Cell #2 : bit position of the reset in the reset control register
39    const: 2
40
41required:
42  - compatible
43
44additionalProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/interrupt-controller/irq.h>
49    #include <dt-bindings/interrupt-controller/arm-gic.h>
50    #include <dt-bindings/clock/hi3660-clock.h>
51
52    iomcu: iomcu@ffd7e000 {
53        compatible = "hisilicon,hi3660-iomcu", "syscon";
54        reg = <0xffd7e000 0x1000>;
55    };
56
57    iomcu_rst: iomcu_rst_controller {
58        compatible = "hisilicon,hi3660-reset";
59        hisilicon,rst-syscon = <&iomcu>;
60        #reset-cells = <2>;
61    };
62
63    /* Specifying reset lines connected to IP modules */
64    i2c@ffd71000 {
65        compatible = "snps,designware-i2c";
66        reg = <0xffd71000 0x1000>;
67        interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
68        #address-cells = <1>;
69        #size-cells = <0>;
70        clock-frequency = <400000>;
71        clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
72        resets = <&iomcu_rst 0x20 3>;
73        pinctrl-names = "default";
74        pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
75        status = "disabled";
76    };
77...
78