1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/qcom,sm8350-pas.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8350/SM8450 Peripheral Authentication Service 8 9maintainers: 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 12description: 13 Qualcomm SM8350/SM8450 SoC Peripheral Authentication Service loads and boots 14 firmware on the Qualcomm DSP Hexagon cores. 15 16properties: 17 compatible: 18 enum: 19 - qcom,sar2130p-adsp-pas 20 - qcom,sm8350-adsp-pas 21 - qcom,sm8350-cdsp-pas 22 - qcom,sm8350-slpi-pas 23 - qcom,sm8350-mpss-pas 24 - qcom,sm8450-adsp-pas 25 - qcom,sm8450-cdsp-pas 26 - qcom,sm8450-mpss-pas 27 - qcom,sm8450-slpi-pas 28 29 reg: 30 maxItems: 1 31 32 clocks: 33 items: 34 - description: XO clock 35 36 clock-names: 37 items: 38 - const: xo 39 40 qcom,qmp: 41 $ref: /schemas/types.yaml#/definitions/phandle 42 description: Reference to the AOSS side-channel message RAM. 43 44 smd-edge: false 45 46 memory-region: 47 maxItems: 1 48 description: Reference to the reserved-memory for the Hexagon core 49 50 firmware-name: 51 maxItems: 1 52 description: Firmware name for the Hexagon core 53 54required: 55 - compatible 56 - reg 57 - memory-region 58 59allOf: 60 - $ref: /schemas/remoteproc/qcom,pas-common.yaml# 61 - if: 62 properties: 63 compatible: 64 enum: 65 - qcom,sar2130p-adsp-pas 66 - qcom,sm8350-adsp-pas 67 - qcom,sm8350-cdsp-pas 68 - qcom,sm8350-slpi-pas 69 - qcom,sm8450-adsp-pas 70 - qcom,sm8450-cdsp-pas 71 - qcom,sm8450-slpi-pas 72 then: 73 properties: 74 interrupts: 75 maxItems: 5 76 interrupt-names: 77 maxItems: 5 78 else: 79 properties: 80 interrupts: 81 minItems: 6 82 interrupt-names: 83 minItems: 6 84 85 - if: 86 properties: 87 compatible: 88 enum: 89 - qcom,sm8350-mpss-pas 90 - qcom,sm8450-mpss-pas 91 then: 92 properties: 93 power-domains: 94 items: 95 - description: CX power domain 96 - description: MSS power domain 97 power-domain-names: 98 items: 99 - const: cx 100 - const: mss 101 102 - if: 103 properties: 104 compatible: 105 enum: 106 - qcom,sar2130p-adsp-pas 107 - qcom,sm8350-adsp-pas 108 - qcom,sm8350-slpi-pas 109 - qcom,sm8450-adsp-pas 110 - qcom,sm8450-slpi-pas 111 then: 112 properties: 113 power-domains: 114 items: 115 - description: LCX power domain 116 - description: LMX power domain 117 power-domain-names: 118 items: 119 - const: lcx 120 - const: lmx 121 122 - if: 123 properties: 124 compatible: 125 enum: 126 - qcom,sm8350-cdsp-pas 127 - qcom,sm8450-cdsp-pas 128 then: 129 properties: 130 power-domains: 131 items: 132 - description: CX power domain 133 - description: MXC power domain 134 power-domain-names: 135 items: 136 - const: cx 137 - const: mxc 138 139unevaluatedProperties: false 140 141examples: 142 - | 143 #include <dt-bindings/clock/qcom,rpmh.h> 144 #include <dt-bindings/interrupt-controller/irq.h> 145 #include <dt-bindings/mailbox/qcom-ipcc.h> 146 #include <dt-bindings/power/qcom,rpmhpd.h> 147 148 remoteproc@30000000 { 149 compatible = "qcom,sm8450-adsp-pas"; 150 reg = <0x030000000 0x100>; 151 152 clocks = <&rpmhcc RPMH_CXO_CLK>; 153 clock-names = "xo"; 154 155 firmware-name = "qcom/sm8450/adsp.mbn"; 156 157 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 158 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 159 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 160 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 161 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 162 interrupt-names = "wdog", "fatal", "ready", 163 "handover", "stop-ack"; 164 165 memory-region = <&adsp_mem>; 166 167 power-domains = <&rpmhpd RPMHPD_LCX>, 168 <&rpmhpd RPMHPD_LMX>; 169 power-domain-names = "lcx", "lmx"; 170 171 qcom,qmp = <&aoss_qmp>; 172 qcom,smem-states = <&smp2p_adsp_out 0>; 173 qcom,smem-state-names = "stop"; 174 175 glink-edge { 176 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 177 IPCC_MPROC_SIGNAL_GLINK_QMP 178 IRQ_TYPE_EDGE_RISING>; 179 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; 180 181 label = "lpass"; 182 qcom,remote-pid = <2>; 183 184 /* ... */ 185 }; 186 }; 187