1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/mtk,scp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek SCP 8 9maintainers: 10 - Tinghan Shen <tinghan.shen@mediatek.com> 11 12description: 13 This binding provides support for ARM Cortex M4 Co-processor found on some 14 Mediatek SoCs. 15 16properties: 17 compatible: 18 enum: 19 - mediatek,mt8183-scp 20 - mediatek,mt8186-scp 21 - mediatek,mt8188-scp 22 - mediatek,mt8192-scp 23 - mediatek,mt8195-scp 24 - mediatek,mt8195-scp-dual 25 26 reg: 27 description: 28 Should contain the address ranges for memory regions SRAM, CFG, and, 29 on some platforms, L1TCM. 30 minItems: 2 31 maxItems: 3 32 33 reg-names: 34 minItems: 2 35 maxItems: 3 36 37 clocks: 38 description: 39 Clock for co-processor (see ../clock/clock-bindings.txt). 40 Required by mt8183 and mt8192. 41 maxItems: 1 42 43 clock-names: 44 const: main 45 46 interrupts: 47 maxItems: 1 48 49 firmware-name: 50 maxItems: 1 51 description: 52 If present, name (or relative path) of the file within the 53 firmware search path containing the firmware image used when 54 initializing SCP. 55 56 memory-region: 57 maxItems: 1 58 59 cros-ec-rpmsg: 60 $ref: /schemas/mfd/google,cros-ec.yaml 61 description: 62 This subnode represents the rpmsg device. The properties 63 of this node are defined by the individual bindings for 64 the rpmsg devices. 65 66 required: 67 - mediatek,rpmsg-name 68 69 unevaluatedProperties: false 70 71 '#address-cells': 72 const: 1 73 74 '#size-cells': 75 const: 1 76 77 ranges: 78 description: 79 Standard ranges definition providing address translations for 80 local SCP SRAM address spaces to bus addresses. 81 82patternProperties: 83 "^scp@[a-f0-9]+$": 84 type: object 85 description: 86 The MediaTek SCP integrated to SoC might be a multi-core version. 87 The other cores are represented as child nodes of the boot core. 88 There are some integration differences for the IP like the usage of 89 address translator for translating SoC bus addresses into address space 90 for the processor. 91 92 Each SCP core has own cache memory. The SRAM and L1TCM are shared by 93 cores. The power of cache, SRAM and L1TCM power should be enabled 94 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied 95 on differnt SoCs. 96 97 The SCP cores do not use an MMU, but has a set of registers to 98 control the translations between 32-bit CPU addresses into system bus 99 addresses. Cache and memory access settings are provided through a 100 Memory Protection Unit (MPU), programmable only from the SCP. 101 102 properties: 103 compatible: 104 enum: 105 - mediatek,scp-core 106 107 reg: 108 description: The base address and size of SRAM. 109 maxItems: 1 110 111 reg-names: 112 const: sram 113 114 interrupts: 115 maxItems: 1 116 117 firmware-name: 118 maxItems: 1 119 description: 120 If present, name (or relative path) of the file within the 121 firmware search path containing the firmware image used when 122 initializing sub cores of multi-core SCP. 123 124 memory-region: 125 maxItems: 1 126 127 cros-ec-rpmsg: 128 $ref: /schemas/mfd/google,cros-ec.yaml 129 description: 130 This subnode represents the rpmsg device. The properties 131 of this node are defined by the individual bindings for 132 the rpmsg devices. 133 134 required: 135 - mediatek,rpmsg-name 136 137 unevaluatedProperties: false 138 139 required: 140 - compatible 141 - reg 142 - reg-names 143 144 additionalProperties: false 145 146required: 147 - compatible 148 - reg 149 - reg-names 150 151allOf: 152 - if: 153 properties: 154 compatible: 155 enum: 156 - mediatek,mt8183-scp 157 - mediatek,mt8192-scp 158 then: 159 required: 160 - clocks 161 - clock-names 162 163 - if: 164 properties: 165 compatible: 166 enum: 167 - mediatek,mt8183-scp 168 - mediatek,mt8186-scp 169 - mediatek,mt8188-scp 170 then: 171 properties: 172 reg: 173 maxItems: 2 174 reg-names: 175 items: 176 - const: sram 177 - const: cfg 178 - if: 179 properties: 180 compatible: 181 enum: 182 - mediatek,mt8192-scp 183 - mediatek,mt8195-scp 184 then: 185 properties: 186 reg: 187 maxItems: 3 188 reg-names: 189 items: 190 - const: sram 191 - const: cfg 192 - const: l1tcm 193 - if: 194 properties: 195 compatible: 196 enum: 197 - mediatek,mt8195-scp-dual 198 then: 199 properties: 200 reg: 201 maxItems: 2 202 reg-names: 203 items: 204 - const: cfg 205 - const: l1tcm 206 207additionalProperties: false 208 209examples: 210 - | 211 #include <dt-bindings/clock/mt8192-clk.h> 212 213 scp@10500000 { 214 compatible = "mediatek,mt8192-scp"; 215 reg = <0x10500000 0x80000>, 216 <0x10700000 0x8000>, 217 <0x10720000 0xe0000>; 218 reg-names = "sram", "cfg", "l1tcm"; 219 clocks = <&infracfg CLK_INFRA_SCPSYS>; 220 clock-names = "main"; 221 222 cros-ec-rpmsg { 223 compatible = "google,cros-ec-rpmsg"; 224 mediatek,rpmsg-name = "cros-ec-rpmsg"; 225 }; 226 }; 227 228 - | 229 scp@10500000 { 230 compatible = "mediatek,mt8195-scp-dual"; 231 reg = <0x10720000 0xe0000>, 232 <0x10700000 0x8000>; 233 reg-names = "cfg", "l1tcm"; 234 235 #address-cells = <1>; 236 #size-cells = <1>; 237 ranges = <0 0x10500000 0x100000>; 238 239 scp@0 { 240 compatible = "mediatek,scp-core"; 241 reg = <0x0 0xa0000>; 242 reg-names = "sram"; 243 244 cros-ec-rpmsg { 245 compatible = "google,cros-ec-rpmsg"; 246 mediatek,rpmsg-name = "cros-ec-rpmsg"; 247 }; 248 }; 249 250 scp@a0000 { 251 compatible = "mediatek,scp-core"; 252 reg = <0xa0000 0x20000>; 253 reg-names = "sram"; 254 255 cros-ec-rpmsg { 256 compatible = "google,cros-ec-rpmsg"; 257 mediatek,rpmsg-name = "cros-ec-rpmsg"; 258 }; 259 }; 260 }; 261