xref: /linux/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml (revision 26fbb4c8c7c3ee9a4c3b4de555a8587b5a19154e)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive PWM controller
9
10maintainers:
11  - Yash Shah <yash.shah@sifive.com>
12  - Sagar Kadam <sagar.kadam@sifive.com>
13  - Paul Walmsley <paul.walmsley@sifive.com>
14
15description:
16  Unlike most other PWM controllers, the SiFive PWM controller currently
17  only supports one period for all channels in the PWM. All PWMs need to
18  run at the same period. The period also has significant restrictions on
19  the values it can achieve, which the driver rounds to the nearest
20  achievable period. PWM RTL that corresponds to the IP block version
21  numbers can be found here -
22
23  https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24
25properties:
26  compatible:
27    items:
28      - const: sifive,fu540-c000-pwm
29      - const: sifive,pwm0
30    description:
31      Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
32      compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
33      as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
34      SiFive PWM v0 IP block with no chip integration tweaks.
35      Please refer to sifive-blocks-ip-versioning.txt for details.
36
37  reg:
38    maxItems: 1
39
40  clocks:
41    maxItems: 1
42
43  "#pwm-cells":
44    const: 3
45
46  interrupts:
47    maxItems: 4
48    description:
49      Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
50
51required:
52  - compatible
53  - reg
54  - clocks
55  - "#pwm-cells"
56  - interrupts
57
58additionalProperties: false
59
60examples:
61  - |
62    pwm:  pwm@10020000 {
63      compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
64      reg = <0x10020000 0x1000>;
65      clocks = <&tlclk>;
66      interrupt-parent = <&plic>;
67      interrupts = <42>, <43>, <44>, <45>;
68      #pwm-cells = <3>;
69    };
70