xref: /linux/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: OpenCores PWM controller
8
9maintainers:
10  - William Qiu <william.qiu@starfivetech.com>
11
12description:
13  The OpenCores PTC ip core contains a PWM controller. When operating in PWM
14  mode, the PTC core generates binary signal with user-programmable low and
15  high periods. All PTC counters and registers are 32-bit.
16
17allOf:
18  - $ref: pwm.yaml#
19
20properties:
21  compatible:
22    items:
23      - enum:
24          - starfive,jh7100-pwm
25          - starfive,jh7110-pwm
26          - starfive,jh8100-pwm
27      - const: opencores,pwm-v1
28
29  reg:
30    maxItems: 1
31
32  clocks:
33    maxItems: 1
34
35  resets:
36    maxItems: 1
37
38  "#pwm-cells":
39    const: 3
40
41required:
42  - compatible
43  - reg
44  - clocks
45
46additionalProperties: false
47
48examples:
49  - |
50    pwm@12490000 {
51        compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
52        reg = <0x12490000 0x10000>;
53        clocks = <&clkgen 181>;
54        resets = <&rstgen 109>;
55        #pwm-cells = <3>;
56    };
57