xref: /linux/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml (revision 336b78c655c84ce9ce47219185171b3912109c0a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek PWM Controller
8
9maintainers:
10  - John Crispin <john@phrozen.org>
11
12allOf:
13  - $ref: pwm.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - enum:
19          - mediatek,mt2712-pwm
20          - mediatek,mt6795-pwm
21          - mediatek,mt7622-pwm
22          - mediatek,mt7623-pwm
23          - mediatek,mt7628-pwm
24          - mediatek,mt7629-pwm
25          - mediatek,mt8183-pwm
26          - mediatek,mt8365-pwm
27          - mediatek,mt8516-pwm
28      - items:
29          - enum:
30              - mediatek,mt8195-pwm
31          - const: mediatek,mt8183-pwm
32
33  reg:
34    maxItems: 1
35
36  "#pwm-cells":
37    const: 2
38
39  interrupts:
40    maxItems: 1
41
42  clocks:
43    minItems: 2
44    maxItems: 10
45
46  clock-names:
47    description:
48      This controller needs two input clocks for its core and one
49      clock for each PWM output.
50    minItems: 2
51    items:
52      - const: top
53      - const: main
54      - const: pwm1
55      - const: pwm2
56      - const: pwm3
57      - const: pwm4
58      - const: pwm5
59      - const: pwm6
60      - const: pwm7
61      - const: pwm8
62
63required:
64  - compatible
65  - reg
66  - "#pwm-cells"
67  - clocks
68  - clock-names
69
70additionalProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/interrupt-controller/arm-gic.h>
75    #include <dt-bindings/clock/mt2712-clk.h>
76    #include <dt-bindings/interrupt-controller/irq.h>
77
78    pwm0: pwm@11006000 {
79        compatible = "mediatek,mt2712-pwm";
80        reg = <0x11006000 0x1000>;
81        #pwm-cells = <2>;
82        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
83        clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,
84                 <&pericfg CLK_PERI_PWM0>, <&pericfg CLK_PERI_PWM1>,
85                 <&pericfg CLK_PERI_PWM2>, <&pericfg CLK_PERI_PWM3>,
86                 <&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>,
87                 <&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>;
88        clock-names = "top", "main",
89                      "pwm1", "pwm2",
90                      "pwm3", "pwm4",
91                      "pwm5", "pwm6",
92                      "pwm7", "pwm8";
93    };
94