1b09b179bSXinlei Lee# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2b09b179bSXinlei Lee%YAML 1.2 3b09b179bSXinlei Lee--- 4b09b179bSXinlei Lee$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml# 5b09b179bSXinlei Lee$schema: http://devicetree.org/meta-schemas/core.yaml# 6b09b179bSXinlei Lee 7dd3cb467SAndrew Lunntitle: MediaTek DISP_PWM Controller 8b09b179bSXinlei Lee 9b09b179bSXinlei Leemaintainers: 10b09b179bSXinlei Lee - Jitao Shi <jitao.shi@mediatek.com> 11b09b179bSXinlei Lee 12b09b179bSXinlei LeeallOf: 13b09b179bSXinlei Lee - $ref: pwm.yaml# 14b09b179bSXinlei Lee 15b09b179bSXinlei Leeproperties: 16b09b179bSXinlei Lee compatible: 17b09b179bSXinlei Lee oneOf: 18b09b179bSXinlei Lee - enum: 19b09b179bSXinlei Lee - mediatek,mt2701-disp-pwm 20b09b179bSXinlei Lee - mediatek,mt6595-disp-pwm 21b09b179bSXinlei Lee - mediatek,mt8173-disp-pwm 22b09b179bSXinlei Lee - mediatek,mt8183-disp-pwm 23b09b179bSXinlei Lee - items: 24c5595335SAngeloGioacchino Del Regno - enum: 25c5595335SAngeloGioacchino Del Regno - mediatek,mt6795-disp-pwm 26c5595335SAngeloGioacchino Del Regno - mediatek,mt8167-disp-pwm 27b09b179bSXinlei Lee - const: mediatek,mt8173-disp-pwm 28b8ba2b42SXinlei Lee - items: 29b8ba2b42SXinlei Lee - enum: 306ddb156bSXinlei Lee - mediatek,mt8186-disp-pwm 316db87be2Sxinlei lee - mediatek,mt8188-disp-pwm 32b8ba2b42SXinlei Lee - mediatek,mt8192-disp-pwm 337eafddceSXinlei Lee - mediatek,mt8195-disp-pwm 34*b3c23dccSAlexandre Mergnat - mediatek,mt8365-disp-pwm 35b8ba2b42SXinlei Lee - const: mediatek,mt8183-disp-pwm 36b09b179bSXinlei Lee 37b09b179bSXinlei Lee reg: 38b09b179bSXinlei Lee maxItems: 1 39b09b179bSXinlei Lee 40b09b179bSXinlei Lee "#pwm-cells": 41b09b179bSXinlei Lee const: 2 42b09b179bSXinlei Lee 432bf8ee0fSXinlei Lee interrupts: 442bf8ee0fSXinlei Lee maxItems: 1 452bf8ee0fSXinlei Lee 46b09b179bSXinlei Lee clocks: 47b09b179bSXinlei Lee items: 48b09b179bSXinlei Lee - description: Main Clock 49b09b179bSXinlei Lee - description: Mm Clock 50b09b179bSXinlei Lee 51b09b179bSXinlei Lee clock-names: 52b09b179bSXinlei Lee items: 53b09b179bSXinlei Lee - const: main 54b09b179bSXinlei Lee - const: mm 55b09b179bSXinlei Lee 56fb7c3d8bSAngeloGioacchino Del Regno power-domains: 57fb7c3d8bSAngeloGioacchino Del Regno maxItems: 1 58fb7c3d8bSAngeloGioacchino Del Regno 59b09b179bSXinlei Leerequired: 60b09b179bSXinlei Lee - compatible 61b09b179bSXinlei Lee - reg 62b09b179bSXinlei Lee - "#pwm-cells" 63b09b179bSXinlei Lee - clocks 64b09b179bSXinlei Lee - clock-names 65b09b179bSXinlei Lee 66b09b179bSXinlei LeeadditionalProperties: false 67b09b179bSXinlei Lee 68b09b179bSXinlei Leeexamples: 69b09b179bSXinlei Lee - | 70b09b179bSXinlei Lee #include <dt-bindings/interrupt-controller/arm-gic.h> 71b09b179bSXinlei Lee #include <dt-bindings/clock/mt8173-clk.h> 72b09b179bSXinlei Lee #include <dt-bindings/interrupt-controller/irq.h> 73b09b179bSXinlei Lee 74b09b179bSXinlei Lee pwm0: pwm@1401e000 { 75b09b179bSXinlei Lee compatible = "mediatek,mt8173-disp-pwm"; 76b09b179bSXinlei Lee reg = <0x1401e000 0x1000>; 77b09b179bSXinlei Lee #pwm-cells = <2>; 78b09b179bSXinlei Lee clocks = <&mmsys CLK_MM_DISP_PWM026M>, 79b09b179bSXinlei Lee <&mmsys CLK_MM_DISP_PWM0MM>; 80b09b179bSXinlei Lee clock-names = "main", "mm"; 81b09b179bSXinlei Lee }; 82