xref: /linux/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml (revision d7f39aee79f04eeaa42085728423501b33ac5be5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale QorIQ 1588 timer based PTP clock
8
9maintainers:
10  - Frank Li <Frank.Li@nxp.com>
11
12properties:
13  compatible:
14    enum:
15      - fsl,etsec-ptp
16      - fsl,fman-ptp-timer
17      - fsl,dpaa2-ptp
18      - fsl,enetc-ptp
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  clocks:
27    maxItems: 1
28
29  fsl,cksel:
30    $ref: /schemas/types.yaml#/definitions/uint32
31    description: |
32      Timer reference clock source.
33
34      Reference clock source is determined by the value, which is holded
35      in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
36      value, which will be directly written in those bits, that is why,
37      according to reference manual, the next clock sources can be used:
38
39      For eTSEC,
40      <0> - external high precision timer reference clock (TSEC_TMR_CLK
41            input is used for this purpose);
42      <1> - eTSEC system clock;
43      <2> - eTSEC1 transmit clock;
44      <3> - RTC clock input.
45
46      For DPAA FMan,
47      <0> - external high precision timer reference clock (TMR_1588_CLK)
48      <1> - MAC system clock (1/2 FMan clock)
49      <2> - reserved
50      <3> - RTC clock oscillator
51
52  fsl,tclk-period:
53    $ref: /schemas/types.yaml#/definitions/uint32
54    description: Timer reference clock period in nanoseconds.
55
56  fsl,tmr-prsc:
57    $ref: /schemas/types.yaml#/definitions/uint32
58    description: Prescaler, divides the output clock.
59
60  fsl,tmr-add:
61    $ref: /schemas/types.yaml#/definitions/uint32
62    description: Frequency compensation value.
63
64  fsl,tmr-fiper1:
65    $ref: /schemas/types.yaml#/definitions/uint32
66    description: Fixed interval period pulse generator.
67
68  fsl,tmr-fiper2:
69    $ref: /schemas/types.yaml#/definitions/uint32
70    description: Fixed interval period pulse generator.
71
72  fsl,tmr-fiper3:
73    $ref: /schemas/types.yaml#/definitions/uint32
74    description:
75      Fixed interval period pulse generator.
76      Supported only on DPAA2 and ENETC hardware.
77
78  fsl,max-adj:
79    $ref: /schemas/types.yaml#/definitions/uint32
80    description: |
81      Maximum frequency adjustment in parts per billion.
82
83      These properties set the operational parameters for the PTP
84      clock. You must choose these carefully for the clock to work right.
85      Here is how to figure good values:
86
87      TimerOsc     = selected reference clock   MHz
88      tclk_period  = desired clock period       nanoseconds
89      NominalFreq  = 1000 / tclk_period         MHz
90      FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
91      tmr_add      = ceil(2^32 / FreqDivRatio)
92      OutputClock  = NominalFreq / tmr_prsc     MHz
93      PulseWidth   = 1 / OutputClock            microseconds
94      FiperFreq1   = desired frequency in Hz
95      FiperDiv1    = 1000000 * OutputClock / FiperFreq1
96      tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
97      max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
98
99      The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
100      driver expects that tmr_fiper1 will be correctly set to produce a 1
101      Pulse Per Second (PPS) signal, since this will be offered to the PPS
102      subsystem to synchronize the Linux clock.
103
104      When this attribute is not used, the IEEE 1588 timer reference clock
105      will use the eTSEC system clock (for Gianfar) or the MAC system
106      clock (for DPAA).
107
108  fsl,extts-fifo:
109    $ref: /schemas/types.yaml#/definitions/flag
110    description:
111      The presence of this property indicates hardware
112      support for the external trigger stamp FIFO
113
114  little-endian:
115    $ref: /schemas/types.yaml#/definitions/flag
116    description:
117      The presence of this property indicates the 1588 timer
118      support for the external trigger stamp FIFO.
119      IP block is little-endian mode. The default endian mode
120      is big-endian.
121
122required:
123  - compatible
124  - reg
125
126additionalProperties: false
127
128examples:
129  - |
130    #include <dt-bindings/interrupt-controller/irq.h>
131
132    phc@24e00 {
133        compatible = "fsl,etsec-ptp";
134        reg = <0x24e00 0xb0>;
135        interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
136        interrupt-parent = <&ipic>;
137        fsl,cksel       = <1>;
138        fsl,tclk-period = <10>;
139        fsl,tmr-prsc    = <100>;
140        fsl,tmr-add     = <0x999999a4>;
141        fsl,tmr-fiper1  = <0x3b9ac9f6>;
142        fsl,tmr-fiper2  = <0x00018696>;
143        fsl,max-adj     = <659999998>;
144    };
145