1Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding 2 3DESCRIPTION 4 5The PAMU is an I/O MMU that provides device-to-memory access control and 6address translation capabilities. 7 8Required properties: 9 10- compatible : <string> 11 First entry is a version-specific string, such as 12 "fsl,pamu-v1.0". The second is "fsl,pamu". 13- ranges : <prop-encoded-array> 14 A standard property. Utilized to describe the memory mapped 15 I/O space utilized by the controller. The size should 16 be set to the total size of the register space of all 17 physically present PAMU controllers. For example, for 18 PAMU v1.0, on an SOC that has five PAMU devices, the size 19 is 0x5000. 20- interrupts : <prop-encoded-array> 21 Interrupt mappings. The first tuple is the normal PAMU 22 interrupt, used for reporting access violations. The second 23 is for PAMU hardware errors, such as PAMU operation errors 24 and ECC errors. 25- #address-cells: <u32> 26 A standard property. 27- #size-cells : <u32> 28 A standard property. 29 30Optional properties: 31- reg : <prop-encoded-array> 32 A standard property. It represents the CCSR registers of 33 all child PAMUs combined. Include it to provide support 34 for legacy drivers. 35- interrupt-parent : <phandle> 36 Phandle to interrupt controller 37- fsl,portid-mapping : <u32> 38 The Coherency Subdomain ID Port Mapping Registers and 39 Snoop ID Port Mapping registers, which are part of the 40 CoreNet Coherency fabric (CCF), provide a CoreNet 41 Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping 42 functions. Certain bits from these registers should be 43 set if PAMUs should be snooped. This property defines 44 a bitmask which selects the bits that should be set if 45 PAMUs should be snooped. 46 47Child nodes: 48 49Each child node represents one PAMU controller. Each SOC device that is 50connected to a specific PAMU device should have a "fsl,pamu-phandle" property 51that links to the corresponding specific child PAMU controller. 52 53- reg : <prop-encoded-array> 54 A standard property. Specifies the physical address and 55 length (relative to the parent 'ranges' property) of this 56 PAMU controller's configuration registers. The size should 57 be set to the size of this PAMU controllers's register space. 58 For PAMU v1.0, this size is 0x1000. 59- fsl,primary-cache-geometry 60 : <prop-encoded-array> 61 Two cells that specify the geometry of the primary PAMU 62 cache. The first is the number of cache lines, and the 63 second is the number of "ways". For direct-mapped caches, 64 specify a value of 1. 65- fsl,secondary-cache-geometry 66 : <prop-encoded-array> 67 Two cells that specify the geometry of the secondary PAMU 68 cache. The first is the number of cache lines, and the 69 second is the number of "ways". For direct-mapped caches, 70 specify a value of 1. 71 72Device nodes: 73 74Devices that have LIODNs need to specify links to the parent PAMU controller 75(the actual PAMU controller that this device is connected to) and a pointer to 76the LIODN register, if applicable. 77 78- fsl,iommu-parent 79 : <phandle> 80 Phandle to the single, specific PAMU controller node to which 81 this device is connect. The PAMU topology is represented in 82 the device tree to assist code that dynamically determines the 83 best LIODN values to minimize PAMU cache thrashing. 84 85- fsl,liodn-reg : <prop-encoded-array> 86 Two cells that specify the location of the LIODN register 87 for this device. Required for devices that have a single 88 LIODN. The first cell is a phandle to a node that contains 89 the registers where the LIODN is to be set. The second is 90 the offset from the first "reg" resource of the node where 91 the specific LIODN register is located. 92 93 94Example: 95 96 iommu@20000 { 97 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 98 reg = <0x20000 0x5000>; 99 ranges = <0 0x20000 0x5000>; 100 fsl,portid-mapping = <0xf80000>; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 interrupts = < 104 24 2 0 0 105 16 2 1 30>; 106 107 pamu0: pamu@0 { 108 reg = <0 0x1000>; 109 fsl,primary-cache-geometry = <32 1>; 110 fsl,secondary-cache-geometry = <128 2>; 111 }; 112 113 pamu1: pamu@1000 { 114 reg = <0x1000 0x1000>; 115 fsl,primary-cache-geometry = <32 1>; 116 fsl,secondary-cache-geometry = <128 2>; 117 }; 118 119 pamu2: pamu@2000 { 120 reg = <0x2000 0x1000>; 121 fsl,primary-cache-geometry = <32 1>; 122 fsl,secondary-cache-geometry = <128 2>; 123 }; 124 125 pamu3: pamu@3000 { 126 reg = <0x3000 0x1000>; 127 fsl,primary-cache-geometry = <32 1>; 128 fsl,secondary-cache-geometry = <128 2>; 129 }; 130 131 pamu4: pamu@4000 { 132 reg = <0x4000 0x1000>; 133 fsl,primary-cache-geometry = <32 1>; 134 fsl,secondary-cache-geometry = <128 2>; 135 }; 136 }; 137 138 guts: global-utilities@e0000 { 139 compatible = "fsl,qoriq-device-config-1.0"; 140 reg = <0xe0000 0xe00>; 141 fsl,has-rstcr; 142 #sleep-cells = <1>; 143 fsl,liodn-bits = <12>; 144 }; 145 146/include/ "qoriq-dma-0.dtsi" 147 dma@100300 { 148 fsl,iommu-parent = <&pamu0>; 149 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */ 150 }; 151