1* Freescale MSI interrupt controller 2 3Required properties: 4- compatible : compatible list, may contain one or two entries 5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, 6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or 7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic 8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is 9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3" 10 should be used. The first entry is optional; the second entry is 11 required. 12 13- reg : It may contain one or two regions. The first region should contain 14 the address and the length of the shared message interrupt register set. 15 The second region should contain the address of aliased MSIIR or MSIIR1 16 register for platforms that have such an alias, if using MSIIR1, the second 17 region must be added because different MSI group has different MSIIR1 offset. 18 19- interrupts : each one of the interrupts here is one entry per 32 MSIs, 20 and routed to the host interrupt controller. the interrupts should 21 be set as edge sensitive. If msi-available-ranges is present, only 22 the interrupts that correspond to available ranges shall be present. 23 24- interrupt-parent: the phandle for the interrupt controller 25 that services interrupts for this device. for 83xx cpu, the interrupts 26 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed 27 to MPIC. 28 29Optional properties: 30- msi-available-ranges: use <start count> style section to define which 31 msi interrupt can be used in the 256 msi interrupts. This property is 32 optional, without this, all the MSI interrupts can be used. 33 Each available range must begin and end on a multiple of 32 (i.e. 34 no splitting an individual MSI register or the associated PIC interrupt). 35 MPIC v4.3 does not support this property because the 32 interrupts of an 36 individual register are not continuous when using MSIIR1. 37 38- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register 39 is used for MSI messaging. The address of MSIIR in PCI address space is 40 the MSI message address. 41 42 This property may be used in virtualized environments where the hypervisor 43 has created an alternate mapping for the MSIR block. See below for an 44 explanation. 45 46 47Example: 48 msi@41600 { 49 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; 50 reg = <0x41600 0x80>; 51 msi-available-ranges = <0 0x100>; 52 interrupts = < 53 0xe0 0 54 0xe1 0 55 0xe2 0 56 0xe3 0 57 0xe4 0 58 0xe5 0 59 0xe6 0 60 0xe7 0>; 61 interrupt-parent = <&mpic>; 62 }; 63 64 msi@41600 { 65 compatible = "fsl,mpic-msi-v4.3"; 66 reg = <0x41600 0x200 0x44148 4>; 67 interrupts = < 68 0xe0 0 0 0 69 0xe1 0 0 0 70 0xe2 0 0 0 71 0xe3 0 0 0 72 0xe4 0 0 0 73 0xe5 0 0 0 74 0xe6 0 0 0 75 0xe7 0 0 0 76 0x100 0 0 0 77 0x101 0 0 0 78 0x102 0 0 0 79 0x103 0 0 0 80 0x104 0 0 0 81 0x105 0 0 0 82 0x106 0 0 0 83 0x107 0 0 0>; 84 }; 85 86The Freescale hypervisor and msi-address-64 87------------------------------------------- 88Normally, PCI devices have access to all of CCSR via an ATMU mapping. The 89Freescale MSI driver calculates the address of MSIIR (in the MSI register 90block) and sets that address as the MSI message address. 91 92In a virtualized environment, the hypervisor may need to create an IOMMU 93mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement 94because of hardware limitations of the Peripheral Access Management Unit 95(PAMU), which is currently the only IOMMU that the hypervisor supports. 96The ATMU is programmed with the guest physical address, and the PAMU 97intercepts transactions and reroutes them to the true physical address. 98 99In the PAMU, each PCI controller is given only one primary window. The 100PAMU restricts DMA operations so that they can only occur within a window. 101Because PCI devices must be able to DMA to memory, the primary window must 102be used to cover all of the guest's memory space. 103 104PAMU primary windows can be divided into 256 subwindows, and each 105subwindow can have its own address mapping ("guest physical" to "true 106physical"). However, each subwindow has to have the same alignment, which 107means they cannot be located at just any address. Because of these 108restrictions, it is usually impossible to create a 4KB subwindow that 109covers MSIIR where it's normally located. 110 111Therefore, the hypervisor has to create a subwindow inside the same 112primary window used for memory, but mapped to the MSIR block (where MSIIR 113lives). The first subwindow after the end of guest memory is used for 114this. The address specified in the msi-address-64 property is the PCI 115address of MSIIR. The hypervisor configures the PAMU to map that address to 116the true physical address of MSIIR. 117