1MPC5121 PSC Device Tree Bindings 2 3PSC in UART mode 4---------------- 5 6For PSC in UART mode the needed PSC serial devices 7are specified by fsl,mpc5121-psc-uart nodes in the 8fsl,mpc5121-immr SoC node. Additionally the PSC FIFO 9Controller node fsl,mpc5121-psc-fifo is required there: 10 11fsl,mpc512x-psc-uart nodes 12-------------------------- 13 14Required properties : 15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc" 16 Supported <soc>s: mpc5121, mpc5125 17 - reg : Offset and length of the register set for the PSC device 18 - interrupts : <a b> where a is the interrupt number of the 19 PSC FIFO Controller and b is a field that represents an 20 encoding of the sense and level information for the interrupt. 21 - interrupt-parent : the phandle for the interrupt controller that 22 services interrupts for this device. 23 24Recommended properties : 25 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) 26 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) 27 28PSC in SPI mode 29--------------- 30 31Similar to the UART mode a PSC can be operated in SPI mode. The compatible used 32for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well. 33The required and recommended properties are identical to the 34fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible 35string. 36 37fsl,mpc512x-psc-fifo node 38------------------------- 39 40Required properties : 41 - compatible : Should be "fsl,<soc>-psc-fifo" 42 Supported <soc>s: mpc5121, mpc5125 43 - reg : Offset and length of the register set for the PSC 44 FIFO Controller 45 - interrupts : <a b> where a is the interrupt number of the 46 PSC FIFO Controller and b is a field that represents an 47 encoding of the sense and level information for the interrupt. 48 - interrupt-parent : the phandle for the interrupt controller that 49 services interrupts for this device. 50 51Recommended properties : 52 - clocks : specifies the clock needed to operate the fifo controller 53 - clock-names : name(s) for the clock(s) listed in clocks 54 55Example for a board using PSC0 and PSC1 devices in serial mode: 56 57serial@11000 { 58 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 59 cell-index = <0>; 60 reg = <0x11000 0x100>; 61 interrupts = <40 0x8>; 62 interrupt-parent = < &ipic >; 63 fsl,rx-fifo-size = <16>; 64 fsl,tx-fifo-size = <16>; 65}; 66 67serial@11100 { 68 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 69 cell-index = <1>; 70 reg = <0x11100 0x100>; 71 interrupts = <40 0x8>; 72 interrupt-parent = < &ipic >; 73 fsl,rx-fifo-size = <16>; 74 fsl,tx-fifo-size = <16>; 75}; 76 77pscfifo@11f00 { 78 compatible = "fsl,mpc5121-psc-fifo"; 79 reg = <0x11f00 0x100>; 80 interrupts = <40 0x8>; 81 interrupt-parent = < &ipic >; 82}; 83