xref: /linux/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml (revision 5f5598d945e2a69f764aa5c2074dad73e23bcfcb)
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Power Domains
8
9maintainers:
10  - Elaine Zhang <zhangqing@rock-chips.com>
11  - Heiko Stuebner <heiko@sntech.de>
12
13description: |
14  Rockchip processors include support for multiple power domains
15  which can be powered up/down by software based on different
16  application scenarios to save power.
17
18  Power domains contained within power-controller node are
19  generic power domain providers documented in
20  Documentation/devicetree/bindings/power/power-domain.yaml.
21
22  IP cores belonging to a power domain should contain a
23  "power-domains" property that is a phandle for the
24  power domain node representing the domain.
25
26properties:
27  $nodename:
28    const: power-controller
29
30  compatible:
31    enum:
32      - rockchip,px30-power-controller
33      - rockchip,rk3036-power-controller
34      - rockchip,rk3066-power-controller
35      - rockchip,rk3128-power-controller
36      - rockchip,rk3188-power-controller
37      - rockchip,rk3228-power-controller
38      - rockchip,rk3288-power-controller
39      - rockchip,rk3328-power-controller
40      - rockchip,rk3366-power-controller
41      - rockchip,rk3368-power-controller
42      - rockchip,rk3399-power-controller
43      - rockchip,rk3528-power-controller
44      - rockchip,rk3562-power-controller
45      - rockchip,rk3568-power-controller
46      - rockchip,rk3576-power-controller
47      - rockchip,rk3588-power-controller
48      - rockchip,rv1126-power-controller
49
50  "#power-domain-cells":
51    const: 1
52
53  "#address-cells":
54    const: 1
55
56  "#size-cells":
57    const: 0
58
59required:
60  - compatible
61  - "#power-domain-cells"
62
63additionalProperties: false
64
65patternProperties:
66  "^power-domain@[0-9a-f]+$":
67
68    $ref: "#/$defs/pd-node"
69
70    unevaluatedProperties: false
71
72    properties:
73      "#address-cells":
74        const: 1
75
76      "#size-cells":
77        const: 0
78
79    patternProperties:
80      "^power-domain@[0-9a-f]+$":
81
82        $ref: "#/$defs/pd-node"
83
84        unevaluatedProperties: false
85
86        properties:
87          "#address-cells":
88            const: 1
89
90          "#size-cells":
91            const: 0
92
93        patternProperties:
94          "^power-domain@[0-9a-f]+$":
95
96            $ref: "#/$defs/pd-node"
97
98            unevaluatedProperties: false
99
100            properties:
101              "#power-domain-cells":
102                const: 0
103
104$defs:
105  pd-node:
106    type: object
107    description: |
108      Represents the power domains within the power controller node.
109
110    properties:
111      reg:
112        maxItems: 1
113        description: |
114          Power domain index. Valid values are defined in
115          "include/dt-bindings/power/px30-power.h"
116          "include/dt-bindings/power/rk3036-power.h"
117          "include/dt-bindings/power/rk3066-power.h"
118          "include/dt-bindings/power/rk3128-power.h"
119          "include/dt-bindings/power/rk3188-power.h"
120          "include/dt-bindings/power/rk3228-power.h"
121          "include/dt-bindings/power/rk3288-power.h"
122          "include/dt-bindings/power/rk3328-power.h"
123          "include/dt-bindings/power/rk3366-power.h"
124          "include/dt-bindings/power/rk3368-power.h"
125          "include/dt-bindings/power/rk3399-power.h"
126          "include/dt-bindings/power/rk3568-power.h"
127          "include/dt-bindings/power/rk3588-power.h"
128          "include/dt-bindings/power/rockchip,rv1126-power.h"
129
130      clocks:
131        minItems: 1
132        maxItems: 30
133        description: |
134          A number of phandles to clocks that need to be enabled
135          while power domain switches state.
136
137      domain-supply:
138        description: domain regulator supply.
139
140      pm_qos:
141        $ref: /schemas/types.yaml#/definitions/phandle-array
142        items:
143          maxItems: 1
144        description: |
145          A number of phandles to qos blocks which need to be saved and restored
146          while power domain switches state.
147
148      "#power-domain-cells":
149        enum: [0, 1]
150        description:
151          Must be 0 for nodes representing a single PM domain and 1 for nodes
152          providing multiple PM domains.
153
154    required:
155      - reg
156      - "#power-domain-cells"
157
158examples:
159  - |
160    #include <dt-bindings/clock/rk3399-cru.h>
161    #include <dt-bindings/power/rk3399-power.h>
162
163    soc {
164        #address-cells = <2>;
165        #size-cells = <2>;
166
167        qos_hdcp: qos@ffa90000 {
168            compatible = "rockchip,rk3399-qos", "syscon";
169            reg = <0x0 0xffa90000 0x0 0x20>;
170        };
171
172        qos_iep: qos@ffa98000 {
173            compatible = "rockchip,rk3399-qos", "syscon";
174            reg = <0x0 0xffa98000 0x0 0x20>;
175        };
176
177        qos_rga_r: qos@ffab0000 {
178            compatible = "rockchip,rk3399-qos", "syscon";
179            reg = <0x0 0xffab0000 0x0 0x20>;
180        };
181
182        qos_rga_w: qos@ffab0080 {
183            compatible = "rockchip,rk3399-qos", "syscon";
184            reg = <0x0 0xffab0080 0x0 0x20>;
185        };
186
187        qos_video_m0: qos@ffab8000 {
188            compatible = "rockchip,rk3399-qos", "syscon";
189            reg = <0x0 0xffab8000 0x0 0x20>;
190        };
191
192        qos_video_m1_r: qos@ffac0000 {
193            compatible = "rockchip,rk3399-qos", "syscon";
194            reg = <0x0 0xffac0000 0x0 0x20>;
195        };
196
197        qos_video_m1_w: qos@ffac0080 {
198            compatible = "rockchip,rk3399-qos", "syscon";
199            reg = <0x0 0xffac0080 0x0 0x20>;
200        };
201
202        power-management@ff310000 {
203            compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
204            reg = <0x0 0xff310000 0x0 0x1000>;
205
206            power-controller {
207                compatible = "rockchip,rk3399-power-controller";
208                #power-domain-cells = <1>;
209                #address-cells = <1>;
210                #size-cells = <0>;
211
212                /* These power domains are grouped by VD_CENTER */
213                power-domain@RK3399_PD_IEP {
214                    reg = <RK3399_PD_IEP>;
215                    clocks = <&cru ACLK_IEP>,
216                             <&cru HCLK_IEP>;
217                    pm_qos = <&qos_iep>;
218                    #power-domain-cells = <0>;
219                };
220                power-domain@RK3399_PD_RGA {
221                    reg = <RK3399_PD_RGA>;
222                    clocks = <&cru ACLK_RGA>,
223                             <&cru HCLK_RGA>;
224                    pm_qos = <&qos_rga_r>,
225                             <&qos_rga_w>;
226                    #power-domain-cells = <0>;
227                };
228                power-domain@RK3399_PD_VCODEC {
229                    reg = <RK3399_PD_VCODEC>;
230                    clocks = <&cru ACLK_VCODEC>,
231                             <&cru HCLK_VCODEC>;
232                    pm_qos = <&qos_video_m0>;
233                    #power-domain-cells = <0>;
234                };
235                power-domain@RK3399_PD_VDU {
236                    reg = <RK3399_PD_VDU>;
237                    clocks = <&cru ACLK_VDU>,
238                             <&cru HCLK_VDU>;
239                    pm_qos = <&qos_video_m1_r>,
240                             <&qos_video_m1_w>;
241                    #power-domain-cells = <0>;
242                };
243                power-domain@RK3399_PD_VIO {
244                    reg = <RK3399_PD_VIO>;
245                    #power-domain-cells = <1>;
246                    #address-cells = <1>;
247                    #size-cells = <0>;
248
249                    power-domain@RK3399_PD_HDCP {
250                        reg = <RK3399_PD_HDCP>;
251                        clocks = <&cru ACLK_HDCP>,
252                                 <&cru HCLK_HDCP>,
253                                 <&cru PCLK_HDCP>;
254                        pm_qos = <&qos_hdcp>;
255                        #power-domain-cells = <0>;
256                    };
257                };
258            };
259        };
260    };
261