xref: /linux/Documentation/devicetree/bindings/power/reset/keystone-reset.txt (revision 24bce201d79807b668bf9d9e0aca801c5c0d5f78) 
1* Device tree bindings for Texas Instruments keystone reset
2
3This node is intended to allow SoC reset in case of software reset
4of selected watchdogs.
5
6The Keystone SoCs can contain up to 4 watchdog timers to reset
7SoC. Each watchdog timer event input is connected to the Reset Mux
8block. The Reset Mux block can be configured to cause reset or not.
9
10Additionally soft or hard reset can be configured.
11
12Required properties:
13
14- compatible:		ti,keystone-reset
15
16- ti,syscon-pll:	phandle/offset pair. The phandle to syscon used to
17			access pll controller registers and the offset to use
18			reset control registers.
19
20- ti,syscon-dev:	phandle/offset pair. The phandle to syscon used to
21			access device state control registers and the offset
22			in order to use mux block registers for all watchdogs.
23
24Optional properties:
25
26- ti,soft-reset:	Boolean option indicating soft reset.
27			By default hard reset is used.
28
29- ti,wdt-list:		WDT list that can cause SoC reset. It's not related
30			to WDT driver, it's just needed to enable a SoC related
31			reset that's triggered by one of WDTs. The list is
32			in format: <0>, <2>; It can be in random order and
33			begins from 0 to 3, as keystone can contain up to 4 SoC
34			reset watchdogs and can be in random order.
35
36Example 1:
37Setup keystone reset so that in case software reset or
38WDT0 is triggered it issues hard reset for SoC.
39
40pllctrl: pll-controller@2310000 {
41	compatible = "ti,keystone-pllctrl", "syscon";
42	reg = <0x02310000 0x200>;
43};
44
45devctrl: device-state-control@2620000 {
46	compatible = "ti,keystone-devctrl", "syscon";
47	reg = <0x02620000 0x1000>;
48};
49
50rstctrl: reset-controller {
51	compatible = "ti,keystone-reset";
52	ti,syscon-pll = <&pllctrl 0xe4>;
53	ti,syscon-dev = <&devctrl 0x328>;
54	ti,wdt-list = <0>;
55};
56
57Example 2:
58Setup keystone reset so that in case of software reset or
59WDT0 or WDT2 is triggered it issues soft reset for SoC.
60
61rstctrl: reset-controller {
62	compatible = "ti,keystone-reset";
63	ti,syscon-pll = <&pllctrl 0xe4>;
64	ti,syscon-dev = <&devctrl 0x328>;
65	ti,wdt-list = <0>, <2>;
66	ti,soft-reset;
67};
68