xref: /linux/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml (revision 94901b7a74d82bfd30420f1d9d00898278fdc8bf) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Power Domains Controller
8
9maintainers:
10  - MandyJH Liu <mandyjh.liu@mediatek.com>
11  - Matthias Brugger <mbrugger@suse.com>
12
13description: |
14  Mediatek processors include support for multiple power domains which can be
15  powered up/down by software based on different application scenes to save power.
16
17  IP cores belonging to a power domain should contain a 'power-domains'
18  property that is a phandle for SCPSYS node representing the domain.
19
20properties:
21  $nodename:
22    pattern: '^power-controller(@[0-9a-f]+)?$'
23
24  compatible:
25    enum:
26      - mediatek,mt6735-power-controller
27      - mediatek,mt6795-power-controller
28      - mediatek,mt8167-power-controller
29      - mediatek,mt8173-power-controller
30      - mediatek,mt8183-power-controller
31      - mediatek,mt8186-power-controller
32      - mediatek,mt8188-power-controller
33      - mediatek,mt8192-power-controller
34      - mediatek,mt8195-power-controller
35      - mediatek,mt8365-power-controller
36
37  '#power-domain-cells':
38    const: 1
39
40  '#address-cells':
41    const: 1
42
43  '#size-cells':
44    const: 0
45
46patternProperties:
47  "^power-domain@[0-9a-f]+$":
48    $ref: "#/$defs/power-domain-node"
49    patternProperties:
50      "^power-domain@[0-9a-f]+$":
51        $ref: "#/$defs/power-domain-node"
52        patternProperties:
53          "^power-domain@[0-9a-f]+$":
54            $ref: "#/$defs/power-domain-node"
55            patternProperties:
56              "^power-domain@[0-9a-f]+$":
57                $ref: "#/$defs/power-domain-node"
58                patternProperties:
59                  "^power-domain@[0-9a-f]+$":
60                    $ref: "#/$defs/power-domain-node"
61                    unevaluatedProperties: false
62                unevaluatedProperties: false
63            unevaluatedProperties: false
64        unevaluatedProperties: false
65    unevaluatedProperties: false
66
67$defs:
68  power-domain-node:
69    type: object
70    description: |
71      Represents the power domains within the power controller node as documented
72      in Documentation/devicetree/bindings/power/power-domain.yaml.
73
74    properties:
75
76      '#power-domain-cells':
77        description:
78          Must be 0 for nodes representing a single PM domain and 1 for nodes
79          providing multiple PM domains.
80
81      '#address-cells':
82        const: 1
83
84      '#size-cells':
85        const: 0
86
87      reg:
88        description: |
89          Power domain index. Valid values are defined in:
90              "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
91              "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
92              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
93              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
94              "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
95              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
96              "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
97              "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
98        maxItems: 1
99
100      clocks:
101        description: |
102          A number of phandles to clocks that need to be enabled during domain
103          power-up sequencing.
104
105      clock-names:
106        description: |
107          List of names of clocks, in order to match the power-up sequencing
108          for each power domain we need to group the clocks by name. BASIC
109          clocks need to be enabled before enabling the corresponding power
110          domain, and should not have a '-' in their name (i.e mm, mfg, venc).
111          SUSBYS clocks need to be enabled before releasing the bus protection,
112          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
113
114          In order to follow properly the power-up sequencing, the clocks must
115          be specified by order, adding first the BASIC clocks followed by the
116          SUSBSYS clocks.
117
118      domain-supply:
119        description: domain regulator supply.
120
121      mediatek,infracfg:
122        $ref: /schemas/types.yaml#/definitions/phandle
123        description: phandle to the device containing the INFRACFG register range.
124
125      mediatek,infracfg-nao:
126        $ref: /schemas/types.yaml#/definitions/phandle
127        description: phandle to the device containing the INFRACFG-NAO register range.
128
129      mediatek,smi:
130        $ref: /schemas/types.yaml#/definitions/phandle
131        description: phandle to the device containing the SMI register range.
132
133    required:
134      - reg
135
136required:
137  - compatible
138
139additionalProperties: false
140
141examples:
142  - |
143    #include <dt-bindings/clock/mt8173-clk.h>
144    #include <dt-bindings/power/mt8173-power.h>
145
146    soc {
147        #address-cells = <2>;
148        #size-cells = <2>;
149
150        scpsys: syscon@10006000 {
151            compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
152            reg = <0 0x10006000 0 0x1000>;
153
154            spm: power-controller {
155                compatible = "mediatek,mt8173-power-controller";
156                #address-cells = <1>;
157                #size-cells = <0>;
158                #power-domain-cells = <1>;
159
160                /* power domains of the SoC */
161                power-domain@MT8173_POWER_DOMAIN_VDEC {
162                    reg = <MT8173_POWER_DOMAIN_VDEC>;
163                    clocks = <&topckgen CLK_TOP_MM_SEL>;
164                    clock-names = "mm";
165                    #power-domain-cells = <0>;
166                };
167                power-domain@MT8173_POWER_DOMAIN_VENC {
168                    reg = <MT8173_POWER_DOMAIN_VENC>;
169                    clocks = <&topckgen CLK_TOP_MM_SEL>,
170                             <&topckgen CLK_TOP_VENC_SEL>;
171                    clock-names = "mm", "venc";
172                    #power-domain-cells = <0>;
173                };
174                power-domain@MT8173_POWER_DOMAIN_ISP {
175                    reg = <MT8173_POWER_DOMAIN_ISP>;
176                    clocks = <&topckgen CLK_TOP_MM_SEL>;
177                    clock-names = "mm";
178                    #power-domain-cells = <0>;
179                };
180                power-domain@MT8173_POWER_DOMAIN_MM {
181                    reg = <MT8173_POWER_DOMAIN_MM>;
182                    clocks = <&topckgen CLK_TOP_MM_SEL>;
183                    clock-names = "mm";
184                    #power-domain-cells = <0>;
185                    mediatek,infracfg = <&infracfg>;
186                };
187                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
188                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
189                    clocks = <&topckgen CLK_TOP_MM_SEL>,
190                             <&topckgen CLK_TOP_VENC_LT_SEL>;
191                    clock-names = "mm", "venclt";
192                    #power-domain-cells = <0>;
193                };
194                power-domain@MT8173_POWER_DOMAIN_AUDIO {
195                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
196                    #power-domain-cells = <0>;
197                };
198                power-domain@MT8173_POWER_DOMAIN_USB {
199                    reg = <MT8173_POWER_DOMAIN_USB>;
200                    #power-domain-cells = <0>;
201                };
202                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
203                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
204                    clocks = <&clk26m>;
205                    clock-names = "mfg";
206                    #address-cells = <1>;
207                    #size-cells = <0>;
208                    #power-domain-cells = <1>;
209
210                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
211                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
212                        #address-cells = <1>;
213                        #size-cells = <0>;
214                        #power-domain-cells = <1>;
215
216                        power-domain@MT8173_POWER_DOMAIN_MFG {
217                            reg = <MT8173_POWER_DOMAIN_MFG>;
218                            #power-domain-cells = <0>;
219                            mediatek,infracfg = <&infracfg>;
220                        };
221                    };
222                };
223            };
224        };
225    };
226