xref: /linux/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml (revision 9208c05f9fdfd927ea160b97dfef3c379049fff2) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Power Domains Controller
8
9maintainers:
10  - MandyJH Liu <mandyjh.liu@mediatek.com>
11  - Matthias Brugger <mbrugger@suse.com>
12
13description: |
14  Mediatek processors include support for multiple power domains which can be
15  powered up/down by software based on different application scenes to save power.
16
17  IP cores belonging to a power domain should contain a 'power-domains'
18  property that is a phandle for SCPSYS node representing the domain.
19
20properties:
21  $nodename:
22    pattern: '^power-controller(@[0-9a-f]+)?$'
23
24  compatible:
25    enum:
26      - mediatek,mt6735-power-controller
27      - mediatek,mt6795-power-controller
28      - mediatek,mt8167-power-controller
29      - mediatek,mt8173-power-controller
30      - mediatek,mt8183-power-controller
31      - mediatek,mt8186-power-controller
32      - mediatek,mt8188-power-controller
33      - mediatek,mt8192-power-controller
34      - mediatek,mt8195-power-controller
35      - mediatek,mt8365-power-controller
36
37  '#power-domain-cells':
38    const: 1
39
40  '#address-cells':
41    const: 1
42
43  '#size-cells':
44    const: 0
45
46patternProperties:
47  "^power-domain@[0-9a-f]+$":
48    $ref: "#/$defs/power-domain-node"
49    patternProperties:
50      "^power-domain@[0-9a-f]+$":
51        $ref: "#/$defs/power-domain-node"
52        patternProperties:
53          "^power-domain@[0-9a-f]+$":
54            $ref: "#/$defs/power-domain-node"
55            patternProperties:
56              "^power-domain@[0-9a-f]+$":
57                $ref: "#/$defs/power-domain-node"
58                unevaluatedProperties: false
59            unevaluatedProperties: false
60        unevaluatedProperties: false
61    unevaluatedProperties: false
62
63$defs:
64  power-domain-node:
65    type: object
66    description: |
67      Represents the power domains within the power controller node as documented
68      in Documentation/devicetree/bindings/power/power-domain.yaml.
69
70    properties:
71
72      '#power-domain-cells':
73        description:
74          Must be 0 for nodes representing a single PM domain and 1 for nodes
75          providing multiple PM domains.
76
77      '#address-cells':
78        const: 1
79
80      '#size-cells':
81        const: 0
82
83      reg:
84        description: |
85          Power domain index. Valid values are defined in:
86              "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
87              "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
88              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
89              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
90              "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
91              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
92              "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
93              "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
94        maxItems: 1
95
96      clocks:
97        description: |
98          A number of phandles to clocks that need to be enabled during domain
99          power-up sequencing.
100
101      clock-names:
102        description: |
103          List of names of clocks, in order to match the power-up sequencing
104          for each power domain we need to group the clocks by name. BASIC
105          clocks need to be enabled before enabling the corresponding power
106          domain, and should not have a '-' in their name (i.e mm, mfg, venc).
107          SUSBYS clocks need to be enabled before releasing the bus protection,
108          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
109
110          In order to follow properly the power-up sequencing, the clocks must
111          be specified by order, adding first the BASIC clocks followed by the
112          SUSBSYS clocks.
113
114      domain-supply:
115        description: domain regulator supply.
116
117      mediatek,infracfg:
118        $ref: /schemas/types.yaml#/definitions/phandle
119        description: phandle to the device containing the INFRACFG register range.
120
121      mediatek,infracfg-nao:
122        $ref: /schemas/types.yaml#/definitions/phandle
123        description: phandle to the device containing the INFRACFG-NAO register range.
124
125      mediatek,smi:
126        $ref: /schemas/types.yaml#/definitions/phandle
127        description: phandle to the device containing the SMI register range.
128
129    required:
130      - reg
131
132required:
133  - compatible
134
135additionalProperties: false
136
137examples:
138  - |
139    #include <dt-bindings/clock/mt8173-clk.h>
140    #include <dt-bindings/power/mt8173-power.h>
141
142    soc {
143        #address-cells = <2>;
144        #size-cells = <2>;
145
146        scpsys: syscon@10006000 {
147            compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
148            reg = <0 0x10006000 0 0x1000>;
149
150            spm: power-controller {
151                compatible = "mediatek,mt8173-power-controller";
152                #address-cells = <1>;
153                #size-cells = <0>;
154                #power-domain-cells = <1>;
155
156                /* power domains of the SoC */
157                power-domain@MT8173_POWER_DOMAIN_VDEC {
158                    reg = <MT8173_POWER_DOMAIN_VDEC>;
159                    clocks = <&topckgen CLK_TOP_MM_SEL>;
160                    clock-names = "mm";
161                    #power-domain-cells = <0>;
162                };
163                power-domain@MT8173_POWER_DOMAIN_VENC {
164                    reg = <MT8173_POWER_DOMAIN_VENC>;
165                    clocks = <&topckgen CLK_TOP_MM_SEL>,
166                             <&topckgen CLK_TOP_VENC_SEL>;
167                    clock-names = "mm", "venc";
168                    #power-domain-cells = <0>;
169                };
170                power-domain@MT8173_POWER_DOMAIN_ISP {
171                    reg = <MT8173_POWER_DOMAIN_ISP>;
172                    clocks = <&topckgen CLK_TOP_MM_SEL>;
173                    clock-names = "mm";
174                    #power-domain-cells = <0>;
175                };
176                power-domain@MT8173_POWER_DOMAIN_MM {
177                    reg = <MT8173_POWER_DOMAIN_MM>;
178                    clocks = <&topckgen CLK_TOP_MM_SEL>;
179                    clock-names = "mm";
180                    #power-domain-cells = <0>;
181                    mediatek,infracfg = <&infracfg>;
182                };
183                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
184                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
185                    clocks = <&topckgen CLK_TOP_MM_SEL>,
186                             <&topckgen CLK_TOP_VENC_LT_SEL>;
187                    clock-names = "mm", "venclt";
188                    #power-domain-cells = <0>;
189                };
190                power-domain@MT8173_POWER_DOMAIN_AUDIO {
191                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
192                    #power-domain-cells = <0>;
193                };
194                power-domain@MT8173_POWER_DOMAIN_USB {
195                    reg = <MT8173_POWER_DOMAIN_USB>;
196                    #power-domain-cells = <0>;
197                };
198                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
199                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
200                    clocks = <&clk26m>;
201                    clock-names = "mfg";
202                    #address-cells = <1>;
203                    #size-cells = <0>;
204                    #power-domain-cells = <1>;
205
206                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
207                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
208                        #address-cells = <1>;
209                        #size-cells = <0>;
210                        #power-domain-cells = <1>;
211
212                        power-domain@MT8173_POWER_DOMAIN_MFG {
213                            reg = <MT8173_POWER_DOMAIN_MFG>;
214                            #power-domain-cells = <0>;
215                            mediatek,infracfg = <&infracfg>;
216                        };
217                    };
218                };
219            };
220        };
221    };
222