1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek Power Domains Controller 8 9maintainers: 10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 11 - Matthias Brugger <mbrugger@suse.com> 12 13description: | 14 Mediatek processors include support for multiple power domains which can be 15 powered up/down by software based on different application scenes to save power. 16 17 IP cores belonging to a power domain should contain a 'power-domains' 18 property that is a phandle for SCPSYS node representing the domain. 19 20properties: 21 $nodename: 22 pattern: '^power-controller(@[0-9a-f]+)?$' 23 24 compatible: 25 enum: 26 - mediatek,mt6735-power-controller 27 - mediatek,mt6795-power-controller 28 - mediatek,mt6893-power-controller 29 - mediatek,mt8167-power-controller 30 - mediatek,mt8173-power-controller 31 - mediatek,mt8183-power-controller 32 - mediatek,mt8186-power-controller 33 - mediatek,mt8188-power-controller 34 - mediatek,mt8189-power-controller 35 - mediatek,mt8192-power-controller 36 - mediatek,mt8195-power-controller 37 - mediatek,mt8196-hwv-hfrp-power-controller 38 - mediatek,mt8196-hwv-scp-power-controller 39 - mediatek,mt8196-power-controller 40 - mediatek,mt8365-power-controller 41 42 '#power-domain-cells': 43 const: 1 44 45 '#address-cells': 46 const: 1 47 48 '#size-cells': 49 const: 0 50 51 access-controllers: 52 description: 53 A number of phandles to external blocks to set and clear the required 54 bits to enable or disable bus protection, necessary to avoid any bus 55 faults while enabling or disabling a power domain. 56 For example, this may hold phandles to INFRACFG and SMI. 57 minItems: 1 58 maxItems: 3 59 60patternProperties: 61 "^power-domain@[0-9a-f]+$": 62 $ref: "#/$defs/power-domain-node" 63 patternProperties: 64 "^power-domain@[0-9a-f]+$": 65 $ref: "#/$defs/power-domain-node" 66 patternProperties: 67 "^power-domain@[0-9a-f]+$": 68 $ref: "#/$defs/power-domain-node" 69 patternProperties: 70 "^power-domain@[0-9a-f]+$": 71 $ref: "#/$defs/power-domain-node" 72 patternProperties: 73 "^power-domain@[0-9a-f]+$": 74 $ref: "#/$defs/power-domain-node" 75 unevaluatedProperties: false 76 unevaluatedProperties: false 77 unevaluatedProperties: false 78 unevaluatedProperties: false 79 unevaluatedProperties: false 80 81$defs: 82 power-domain-node: 83 type: object 84 description: | 85 Represents the power domains within the power controller node as documented 86 in Documentation/devicetree/bindings/power/power-domain.yaml. 87 88 properties: 89 90 '#power-domain-cells': 91 description: 92 Must be 0 for nodes representing a single PM domain and 1 for nodes 93 providing multiple PM domains. 94 95 '#address-cells': 96 const: 1 97 98 '#size-cells': 99 const: 0 100 101 reg: 102 description: | 103 Power domain index. Valid values are defined in: 104 "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. 105 "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. 106 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. 107 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. 108 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. 109 "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain. 110 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. 111 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. 112 "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain. 113 maxItems: 1 114 115 clocks: 116 description: | 117 A number of phandles to clocks that need to be enabled during domain 118 power-up sequencing. 119 120 clock-names: 121 description: | 122 List of names of clocks, in order to match the power-up sequencing 123 for each power domain we need to group the clocks by name. BASIC 124 clocks need to be enabled before enabling the corresponding power 125 domain, and should not have a '-' in their name (i.e mm, mfg, venc). 126 SUSBYS clocks need to be enabled before releasing the bus protection, 127 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). 128 129 In order to follow properly the power-up sequencing, the clocks must 130 be specified by order, adding first the BASIC clocks followed by the 131 SUSBSYS clocks. 132 133 domain-supply: 134 description: domain regulator supply. 135 136 mediatek,infracfg: 137 $ref: /schemas/types.yaml#/definitions/phandle 138 description: phandle to the device containing the INFRACFG register range. 139 deprecated: true 140 141 mediatek,infracfg-nao: 142 $ref: /schemas/types.yaml#/definitions/phandle 143 description: phandle to the device containing the INFRACFG-NAO register range. 144 deprecated: true 145 146 mediatek,smi: 147 $ref: /schemas/types.yaml#/definitions/phandle 148 description: phandle to the device containing the SMI register range. 149 deprecated: true 150 151 required: 152 - reg 153 154required: 155 - compatible 156 157allOf: 158 - if: 159 properties: 160 compatible: 161 contains: 162 enum: 163 - mediatek,mt8183-power-controller 164 - mediatek,mt8196-power-controller 165 then: 166 properties: 167 access-controllers: 168 minItems: 2 169 maxItems: 2 170 171 - if: 172 properties: 173 compatible: 174 contains: 175 enum: 176 - mediatek,mt8365-power-controller 177 then: 178 properties: 179 access-controllers: 180 minItems: 3 181 maxItems: 3 182 183additionalProperties: false 184 185examples: 186 - | 187 #include <dt-bindings/clock/mt8173-clk.h> 188 #include <dt-bindings/power/mt8173-power.h> 189 190 soc { 191 #address-cells = <2>; 192 #size-cells = <2>; 193 194 scpsys: syscon@10006000 { 195 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; 196 reg = <0 0x10006000 0 0x1000>; 197 198 spm: power-controller { 199 compatible = "mediatek,mt8173-power-controller"; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 #power-domain-cells = <1>; 203 204 /* power domains of the SoC */ 205 power-domain@MT8173_POWER_DOMAIN_VDEC { 206 reg = <MT8173_POWER_DOMAIN_VDEC>; 207 clocks = <&topckgen CLK_TOP_MM_SEL>; 208 clock-names = "mm"; 209 #power-domain-cells = <0>; 210 }; 211 power-domain@MT8173_POWER_DOMAIN_VENC { 212 reg = <MT8173_POWER_DOMAIN_VENC>; 213 clocks = <&topckgen CLK_TOP_MM_SEL>, 214 <&topckgen CLK_TOP_VENC_SEL>; 215 clock-names = "mm", "venc"; 216 #power-domain-cells = <0>; 217 }; 218 power-domain@MT8173_POWER_DOMAIN_ISP { 219 reg = <MT8173_POWER_DOMAIN_ISP>; 220 clocks = <&topckgen CLK_TOP_MM_SEL>; 221 clock-names = "mm"; 222 #power-domain-cells = <0>; 223 }; 224 power-domain@MT8173_POWER_DOMAIN_MM { 225 reg = <MT8173_POWER_DOMAIN_MM>; 226 clocks = <&topckgen CLK_TOP_MM_SEL>; 227 clock-names = "mm"; 228 #power-domain-cells = <0>; 229 mediatek,infracfg = <&infracfg>; 230 }; 231 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 232 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 233 clocks = <&topckgen CLK_TOP_MM_SEL>, 234 <&topckgen CLK_TOP_VENC_LT_SEL>; 235 clock-names = "mm", "venclt"; 236 #power-domain-cells = <0>; 237 }; 238 power-domain@MT8173_POWER_DOMAIN_AUDIO { 239 reg = <MT8173_POWER_DOMAIN_AUDIO>; 240 #power-domain-cells = <0>; 241 }; 242 power-domain@MT8173_POWER_DOMAIN_USB { 243 reg = <MT8173_POWER_DOMAIN_USB>; 244 #power-domain-cells = <0>; 245 }; 246 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 247 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 248 clocks = <&clk26m>; 249 clock-names = "mfg"; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 #power-domain-cells = <1>; 253 254 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 255 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 #power-domain-cells = <1>; 259 260 power-domain@MT8173_POWER_DOMAIN_MFG { 261 reg = <MT8173_POWER_DOMAIN_MFG>; 262 #power-domain-cells = <0>; 263 mediatek,infracfg = <&infracfg>; 264 }; 265 }; 266 }; 267 }; 268 }; 269 }; 270