1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek Power Domains Controller 8 9maintainers: 10 - MandyJH Liu <mandyjh.liu@mediatek.com> 11 - Matthias Brugger <mbrugger@suse.com> 12 13description: | 14 Mediatek processors include support for multiple power domains which can be 15 powered up/down by software based on different application scenes to save power. 16 17 IP cores belonging to a power domain should contain a 'power-domains' 18 property that is a phandle for SCPSYS node representing the domain. 19 20properties: 21 $nodename: 22 pattern: '^power-controller(@[0-9a-f]+)?$' 23 24 compatible: 25 enum: 26 - mediatek,mt6735-power-controller 27 - mediatek,mt6795-power-controller 28 - mediatek,mt6893-power-controller 29 - mediatek,mt8167-power-controller 30 - mediatek,mt8173-power-controller 31 - mediatek,mt8183-power-controller 32 - mediatek,mt8186-power-controller 33 - mediatek,mt8188-power-controller 34 - mediatek,mt8192-power-controller 35 - mediatek,mt8195-power-controller 36 - mediatek,mt8196-hwv-hfrp-power-controller 37 - mediatek,mt8196-hwv-scp-power-controller 38 - mediatek,mt8196-power-controller 39 - mediatek,mt8365-power-controller 40 41 '#power-domain-cells': 42 const: 1 43 44 '#address-cells': 45 const: 1 46 47 '#size-cells': 48 const: 0 49 50 access-controllers: 51 description: 52 A number of phandles to external blocks to set and clear the required 53 bits to enable or disable bus protection, necessary to avoid any bus 54 faults while enabling or disabling a power domain. 55 For example, this may hold phandles to INFRACFG and SMI. 56 minItems: 1 57 maxItems: 3 58 59patternProperties: 60 "^power-domain@[0-9a-f]+$": 61 $ref: "#/$defs/power-domain-node" 62 patternProperties: 63 "^power-domain@[0-9a-f]+$": 64 $ref: "#/$defs/power-domain-node" 65 patternProperties: 66 "^power-domain@[0-9a-f]+$": 67 $ref: "#/$defs/power-domain-node" 68 patternProperties: 69 "^power-domain@[0-9a-f]+$": 70 $ref: "#/$defs/power-domain-node" 71 patternProperties: 72 "^power-domain@[0-9a-f]+$": 73 $ref: "#/$defs/power-domain-node" 74 unevaluatedProperties: false 75 unevaluatedProperties: false 76 unevaluatedProperties: false 77 unevaluatedProperties: false 78 unevaluatedProperties: false 79 80$defs: 81 power-domain-node: 82 type: object 83 description: | 84 Represents the power domains within the power controller node as documented 85 in Documentation/devicetree/bindings/power/power-domain.yaml. 86 87 properties: 88 89 '#power-domain-cells': 90 description: 91 Must be 0 for nodes representing a single PM domain and 1 for nodes 92 providing multiple PM domains. 93 94 '#address-cells': 95 const: 1 96 97 '#size-cells': 98 const: 0 99 100 reg: 101 description: | 102 Power domain index. Valid values are defined in: 103 "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. 104 "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. 105 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. 106 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. 107 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. 108 "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain. 109 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. 110 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. 111 "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain. 112 maxItems: 1 113 114 clocks: 115 description: | 116 A number of phandles to clocks that need to be enabled during domain 117 power-up sequencing. 118 119 clock-names: 120 description: | 121 List of names of clocks, in order to match the power-up sequencing 122 for each power domain we need to group the clocks by name. BASIC 123 clocks need to be enabled before enabling the corresponding power 124 domain, and should not have a '-' in their name (i.e mm, mfg, venc). 125 SUSBYS clocks need to be enabled before releasing the bus protection, 126 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). 127 128 In order to follow properly the power-up sequencing, the clocks must 129 be specified by order, adding first the BASIC clocks followed by the 130 SUSBSYS clocks. 131 132 domain-supply: 133 description: domain regulator supply. 134 135 mediatek,infracfg: 136 $ref: /schemas/types.yaml#/definitions/phandle 137 description: phandle to the device containing the INFRACFG register range. 138 deprecated: true 139 140 mediatek,infracfg-nao: 141 $ref: /schemas/types.yaml#/definitions/phandle 142 description: phandle to the device containing the INFRACFG-NAO register range. 143 deprecated: true 144 145 mediatek,smi: 146 $ref: /schemas/types.yaml#/definitions/phandle 147 description: phandle to the device containing the SMI register range. 148 deprecated: true 149 150 required: 151 - reg 152 153required: 154 - compatible 155 156allOf: 157 - if: 158 properties: 159 compatible: 160 contains: 161 enum: 162 - mediatek,mt8183-power-controller 163 - mediatek,mt8196-power-controller 164 then: 165 properties: 166 access-controllers: 167 minItems: 2 168 maxItems: 2 169 170 - if: 171 properties: 172 compatible: 173 contains: 174 enum: 175 - mediatek,mt8365-power-controller 176 then: 177 properties: 178 access-controllers: 179 minItems: 3 180 maxItems: 3 181 182additionalProperties: false 183 184examples: 185 - | 186 #include <dt-bindings/clock/mt8173-clk.h> 187 #include <dt-bindings/power/mt8173-power.h> 188 189 soc { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 193 scpsys: syscon@10006000 { 194 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; 195 reg = <0 0x10006000 0 0x1000>; 196 197 spm: power-controller { 198 compatible = "mediatek,mt8173-power-controller"; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 #power-domain-cells = <1>; 202 203 /* power domains of the SoC */ 204 power-domain@MT8173_POWER_DOMAIN_VDEC { 205 reg = <MT8173_POWER_DOMAIN_VDEC>; 206 clocks = <&topckgen CLK_TOP_MM_SEL>; 207 clock-names = "mm"; 208 #power-domain-cells = <0>; 209 }; 210 power-domain@MT8173_POWER_DOMAIN_VENC { 211 reg = <MT8173_POWER_DOMAIN_VENC>; 212 clocks = <&topckgen CLK_TOP_MM_SEL>, 213 <&topckgen CLK_TOP_VENC_SEL>; 214 clock-names = "mm", "venc"; 215 #power-domain-cells = <0>; 216 }; 217 power-domain@MT8173_POWER_DOMAIN_ISP { 218 reg = <MT8173_POWER_DOMAIN_ISP>; 219 clocks = <&topckgen CLK_TOP_MM_SEL>; 220 clock-names = "mm"; 221 #power-domain-cells = <0>; 222 }; 223 power-domain@MT8173_POWER_DOMAIN_MM { 224 reg = <MT8173_POWER_DOMAIN_MM>; 225 clocks = <&topckgen CLK_TOP_MM_SEL>; 226 clock-names = "mm"; 227 #power-domain-cells = <0>; 228 mediatek,infracfg = <&infracfg>; 229 }; 230 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 231 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 232 clocks = <&topckgen CLK_TOP_MM_SEL>, 233 <&topckgen CLK_TOP_VENC_LT_SEL>; 234 clock-names = "mm", "venclt"; 235 #power-domain-cells = <0>; 236 }; 237 power-domain@MT8173_POWER_DOMAIN_AUDIO { 238 reg = <MT8173_POWER_DOMAIN_AUDIO>; 239 #power-domain-cells = <0>; 240 }; 241 power-domain@MT8173_POWER_DOMAIN_USB { 242 reg = <MT8173_POWER_DOMAIN_USB>; 243 #power-domain-cells = <0>; 244 }; 245 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 246 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 247 clocks = <&clk26m>; 248 clock-names = "mfg"; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 #power-domain-cells = <1>; 252 253 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 254 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 #power-domain-cells = <1>; 258 259 power-domain@MT8173_POWER_DOMAIN_MFG { 260 reg = <MT8173_POWER_DOMAIN_MFG>; 261 #power-domain-cells = <0>; 262 mediatek,infracfg = <&infracfg>; 263 }; 264 }; 265 }; 266 }; 267 }; 268 }; 269