xref: /linux/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Power Domains Controller
8
9maintainers:
10  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11  - Matthias Brugger <mbrugger@suse.com>
12
13description: |
14  Mediatek processors include support for multiple power domains which can be
15  powered up/down by software based on different application scenes to save power.
16
17  IP cores belonging to a power domain should contain a 'power-domains'
18  property that is a phandle for SCPSYS node representing the domain.
19
20properties:
21  $nodename:
22    pattern: '^power-controller(@[0-9a-f]+)?$'
23
24  compatible:
25    enum:
26      - mediatek,mt6735-power-controller
27      - mediatek,mt6795-power-controller
28      - mediatek,mt6858-power-controller
29      - mediatek,mt6893-power-controller
30      - mediatek,mt8167-power-controller
31      - mediatek,mt8173-power-controller
32      - mediatek,mt8183-power-controller
33      - mediatek,mt8186-power-controller
34      - mediatek,mt8188-power-controller
35      - mediatek,mt8189-power-controller
36      - mediatek,mt8192-power-controller
37      - mediatek,mt8195-power-controller
38      - mediatek,mt8196-hfrp-power-controller
39      - mediatek,mt8196-hwv-hfrp-power-controller
40      - mediatek,mt8196-hwv-scp-power-controller
41      - mediatek,mt8196-power-controller
42      - mediatek,mt8365-power-controller
43
44  '#power-domain-cells':
45    const: 1
46
47  '#address-cells':
48    const: 1
49
50  '#size-cells':
51    const: 0
52
53  access-controllers:
54    description:
55      A number of phandles to external blocks to set and clear the required
56      bits to enable or disable bus protection, necessary to avoid any bus
57      faults while enabling or disabling a power domain.
58      For example, this may hold phandles to INFRACFG and SMI.
59    minItems: 1
60    maxItems: 6
61
62patternProperties:
63  "^power-domain@[0-9a-f]+$":
64    $ref: "#/$defs/power-domain-node"
65    patternProperties:
66      "^power-domain@[0-9a-f]+$":
67        $ref: "#/$defs/power-domain-node"
68        patternProperties:
69          "^power-domain@[0-9a-f]+$":
70            $ref: "#/$defs/power-domain-node"
71            patternProperties:
72              "^power-domain@[0-9a-f]+$":
73                $ref: "#/$defs/power-domain-node"
74                patternProperties:
75                  "^power-domain@[0-9a-f]+$":
76                    $ref: "#/$defs/power-domain-node"
77                    unevaluatedProperties: false
78                unevaluatedProperties: false
79            unevaluatedProperties: false
80        unevaluatedProperties: false
81    unevaluatedProperties: false
82
83$defs:
84  power-domain-node:
85    type: object
86    description: |
87      Represents the power domains within the power controller node as documented
88      in Documentation/devicetree/bindings/power/power-domain.yaml.
89
90    properties:
91
92      '#power-domain-cells':
93        description:
94          Must be 0 for nodes representing a single PM domain and 1 for nodes
95          providing multiple PM domains.
96
97      '#address-cells':
98        const: 1
99
100      '#size-cells':
101        const: 0
102
103      reg:
104        description: |
105          Power domain index. Valid values are defined in:
106              "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
107              "include/dt-bindings/power/mediatek,mt6858-power.h" - for MT6858 type power domain.
108              "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain.
109              "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
110              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
111              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
112              "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
113              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
114              "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
115              "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
116        maxItems: 1
117
118      clocks:
119        description: |
120          A number of phandles to clocks that need to be enabled during domain
121          power-up sequencing.
122
123      clock-names:
124        description: |
125          List of names of clocks, in order to match the power-up sequencing
126          for each power domain we need to group the clocks by name. BASIC
127          clocks need to be enabled before enabling the corresponding power
128          domain, and should not have a '-' in their name (i.e mm, mfg, venc).
129          SUSBYS clocks need to be enabled before releasing the bus protection,
130          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
131
132          In order to follow properly the power-up sequencing, the clocks must
133          be specified by order, adding first the BASIC clocks followed by the
134          SUSBSYS clocks.
135
136      domain-supply:
137        description: domain regulator supply.
138
139      mediatek,infracfg:
140        $ref: /schemas/types.yaml#/definitions/phandle
141        description: phandle to the device containing the INFRACFG register range.
142        deprecated: true
143
144      mediatek,infracfg-nao:
145        $ref: /schemas/types.yaml#/definitions/phandle
146        description: phandle to the device containing the INFRACFG-NAO register range.
147        deprecated: true
148
149      mediatek,smi:
150        $ref: /schemas/types.yaml#/definitions/phandle
151        description: phandle to the device containing the SMI register range.
152        deprecated: true
153
154    required:
155      - reg
156
157required:
158  - compatible
159
160allOf:
161  - if:
162      properties:
163        compatible:
164          contains:
165            enum:
166              - mediatek,mt6858-power-controller
167    then:
168      properties:
169        access-controllers:
170          items:
171            - description: handle to INFRACFG register block
172            - description: handle to IMG_SUB0 register block
173            - description: handle to CAM_SUB1 register block
174            - description: handle to CAM_SUB0 register block
175            - description: handle to IPE_SUB0 register block
176            - description: handle to VLPCFG register block
177
178  - if:
179      properties:
180        compatible:
181          contains:
182            enum:
183              - mediatek,mt8183-power-controller
184              - mediatek,mt8196-power-controller
185    then:
186      properties:
187        access-controllers:
188          minItems: 2
189          maxItems: 2
190
191  - if:
192      properties:
193        compatible:
194          contains:
195            enum:
196              - mediatek,mt8365-power-controller
197    then:
198      properties:
199        access-controllers:
200          minItems: 3
201          maxItems: 3
202
203additionalProperties: false
204
205examples:
206  - |
207    #include <dt-bindings/clock/mt8173-clk.h>
208    #include <dt-bindings/power/mt8173-power.h>
209
210    soc {
211        #address-cells = <2>;
212        #size-cells = <2>;
213
214        scpsys: syscon@10006000 {
215            compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
216            reg = <0 0x10006000 0 0x1000>;
217
218            spm: power-controller {
219                compatible = "mediatek,mt8173-power-controller";
220                #address-cells = <1>;
221                #size-cells = <0>;
222                #power-domain-cells = <1>;
223
224                /* power domains of the SoC */
225                power-domain@MT8173_POWER_DOMAIN_VDEC {
226                    reg = <MT8173_POWER_DOMAIN_VDEC>;
227                    clocks = <&topckgen CLK_TOP_MM_SEL>;
228                    clock-names = "mm";
229                    #power-domain-cells = <0>;
230                };
231                power-domain@MT8173_POWER_DOMAIN_VENC {
232                    reg = <MT8173_POWER_DOMAIN_VENC>;
233                    clocks = <&topckgen CLK_TOP_MM_SEL>,
234                             <&topckgen CLK_TOP_VENC_SEL>;
235                    clock-names = "mm", "venc";
236                    #power-domain-cells = <0>;
237                };
238                power-domain@MT8173_POWER_DOMAIN_ISP {
239                    reg = <MT8173_POWER_DOMAIN_ISP>;
240                    clocks = <&topckgen CLK_TOP_MM_SEL>;
241                    clock-names = "mm";
242                    #power-domain-cells = <0>;
243                };
244                power-domain@MT8173_POWER_DOMAIN_MM {
245                    reg = <MT8173_POWER_DOMAIN_MM>;
246                    clocks = <&topckgen CLK_TOP_MM_SEL>;
247                    clock-names = "mm";
248                    #power-domain-cells = <0>;
249                    mediatek,infracfg = <&infracfg>;
250                };
251                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
252                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
253                    clocks = <&topckgen CLK_TOP_MM_SEL>,
254                             <&topckgen CLK_TOP_VENC_LT_SEL>;
255                    clock-names = "mm", "venclt";
256                    #power-domain-cells = <0>;
257                };
258                power-domain@MT8173_POWER_DOMAIN_AUDIO {
259                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
260                    #power-domain-cells = <0>;
261                };
262                power-domain@MT8173_POWER_DOMAIN_USB {
263                    reg = <MT8173_POWER_DOMAIN_USB>;
264                    #power-domain-cells = <0>;
265                };
266                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
267                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
268                    clocks = <&clk26m>;
269                    clock-names = "mfg";
270                    #address-cells = <1>;
271                    #size-cells = <0>;
272                    #power-domain-cells = <1>;
273
274                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
275                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
276                        #address-cells = <1>;
277                        #size-cells = <0>;
278                        #power-domain-cells = <1>;
279
280                        power-domain@MT8173_POWER_DOMAIN_MFG {
281                            reg = <MT8173_POWER_DOMAIN_MFG>;
282                            #power-domain-cells = <0>;
283                            mediatek,infracfg = <&infracfg>;
284                        };
285                    };
286                };
287            };
288        };
289    };
290