xref: /linux/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Power Domains Controller
8
9maintainers:
10  - MandyJH Liu <mandyjh.liu@mediatek.com>
11  - Matthias Brugger <mbrugger@suse.com>
12
13description: |
14  Mediatek processors include support for multiple power domains which can be
15  powered up/down by software based on different application scenes to save power.
16
17  IP cores belonging to a power domain should contain a 'power-domains'
18  property that is a phandle for SCPSYS node representing the domain.
19
20properties:
21  $nodename:
22    pattern: '^power-controller(@[0-9a-f]+)?$'
23
24  compatible:
25    enum:
26      - mediatek,mt6795-power-controller
27      - mediatek,mt8167-power-controller
28      - mediatek,mt8173-power-controller
29      - mediatek,mt8183-power-controller
30      - mediatek,mt8186-power-controller
31      - mediatek,mt8188-power-controller
32      - mediatek,mt8192-power-controller
33      - mediatek,mt8195-power-controller
34
35  '#power-domain-cells':
36    const: 1
37
38  '#address-cells':
39    const: 1
40
41  '#size-cells':
42    const: 0
43
44patternProperties:
45  "^power-domain@[0-9a-f]+$":
46    $ref: "#/$defs/power-domain-node"
47    patternProperties:
48      "^power-domain@[0-9a-f]+$":
49        $ref: "#/$defs/power-domain-node"
50        patternProperties:
51          "^power-domain@[0-9a-f]+$":
52            $ref: "#/$defs/power-domain-node"
53            patternProperties:
54              "^power-domain@[0-9a-f]+$":
55                $ref: "#/$defs/power-domain-node"
56                unevaluatedProperties: false
57            unevaluatedProperties: false
58        unevaluatedProperties: false
59    unevaluatedProperties: false
60
61$defs:
62  power-domain-node:
63    type: object
64    description: |
65      Represents the power domains within the power controller node as documented
66      in Documentation/devicetree/bindings/power/power-domain.yaml.
67
68    properties:
69
70      '#power-domain-cells':
71        description:
72          Must be 0 for nodes representing a single PM domain and 1 for nodes
73          providing multiple PM domains.
74
75      '#address-cells':
76        const: 1
77
78      '#size-cells':
79        const: 0
80
81      reg:
82        description: |
83          Power domain index. Valid values are defined in:
84              "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
85              "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
86              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
87              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
88              "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
89              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
90              "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
91        maxItems: 1
92
93      clocks:
94        description: |
95          A number of phandles to clocks that need to be enabled during domain
96          power-up sequencing.
97
98      clock-names:
99        description: |
100          List of names of clocks, in order to match the power-up sequencing
101          for each power domain we need to group the clocks by name. BASIC
102          clocks need to be enabled before enabling the corresponding power
103          domain, and should not have a '-' in their name (i.e mm, mfg, venc).
104          SUSBYS clocks need to be enabled before releasing the bus protection,
105          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
106
107          In order to follow properly the power-up sequencing, the clocks must
108          be specified by order, adding first the BASIC clocks followed by the
109          SUSBSYS clocks.
110
111      domain-supply:
112        description: domain regulator supply.
113
114      mediatek,infracfg:
115        $ref: /schemas/types.yaml#/definitions/phandle
116        description: phandle to the device containing the INFRACFG register range.
117
118      mediatek,smi:
119        $ref: /schemas/types.yaml#/definitions/phandle
120        description: phandle to the device containing the SMI register range.
121
122    required:
123      - reg
124
125required:
126  - compatible
127
128additionalProperties: false
129
130examples:
131  - |
132    #include <dt-bindings/clock/mt8173-clk.h>
133    #include <dt-bindings/power/mt8173-power.h>
134
135    soc {
136        #address-cells = <2>;
137        #size-cells = <2>;
138
139        scpsys: syscon@10006000 {
140            compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
141            reg = <0 0x10006000 0 0x1000>;
142
143            spm: power-controller {
144                compatible = "mediatek,mt8173-power-controller";
145                #address-cells = <1>;
146                #size-cells = <0>;
147                #power-domain-cells = <1>;
148
149                /* power domains of the SoC */
150                power-domain@MT8173_POWER_DOMAIN_VDEC {
151                    reg = <MT8173_POWER_DOMAIN_VDEC>;
152                    clocks = <&topckgen CLK_TOP_MM_SEL>;
153                    clock-names = "mm";
154                    #power-domain-cells = <0>;
155                };
156                power-domain@MT8173_POWER_DOMAIN_VENC {
157                    reg = <MT8173_POWER_DOMAIN_VENC>;
158                    clocks = <&topckgen CLK_TOP_MM_SEL>,
159                             <&topckgen CLK_TOP_VENC_SEL>;
160                    clock-names = "mm", "venc";
161                    #power-domain-cells = <0>;
162                };
163                power-domain@MT8173_POWER_DOMAIN_ISP {
164                    reg = <MT8173_POWER_DOMAIN_ISP>;
165                    clocks = <&topckgen CLK_TOP_MM_SEL>;
166                    clock-names = "mm";
167                    #power-domain-cells = <0>;
168                };
169                power-domain@MT8173_POWER_DOMAIN_MM {
170                    reg = <MT8173_POWER_DOMAIN_MM>;
171                    clocks = <&topckgen CLK_TOP_MM_SEL>;
172                    clock-names = "mm";
173                    #power-domain-cells = <0>;
174                    mediatek,infracfg = <&infracfg>;
175                };
176                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
177                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
178                    clocks = <&topckgen CLK_TOP_MM_SEL>,
179                             <&topckgen CLK_TOP_VENC_LT_SEL>;
180                    clock-names = "mm", "venclt";
181                    #power-domain-cells = <0>;
182                };
183                power-domain@MT8173_POWER_DOMAIN_AUDIO {
184                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
185                    #power-domain-cells = <0>;
186                };
187                power-domain@MT8173_POWER_DOMAIN_USB {
188                    reg = <MT8173_POWER_DOMAIN_USB>;
189                    #power-domain-cells = <0>;
190                };
191                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
192                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
193                    clocks = <&clk26m>;
194                    clock-names = "mfg";
195                    #address-cells = <1>;
196                    #size-cells = <0>;
197                    #power-domain-cells = <1>;
198
199                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
200                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
201                        #address-cells = <1>;
202                        #size-cells = <0>;
203                        #power-domain-cells = <1>;
204
205                        power-domain@MT8173_POWER_DOMAIN_MFG {
206                            reg = <MT8173_POWER_DOMAIN_MFG>;
207                            #power-domain-cells = <0>;
208                            mediatek,infracfg = <&infracfg>;
209                        };
210                    };
211                };
212            };
213        };
214    };
215