1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek Power Domains Controller 8 9maintainers: 10 - MandyJH Liu <mandyjh.liu@mediatek.com> 11 - Matthias Brugger <mbrugger@suse.com> 12 13description: | 14 Mediatek processors include support for multiple power domains which can be 15 powered up/down by software based on different application scenes to save power. 16 17 IP cores belonging to a power domain should contain a 'power-domains' 18 property that is a phandle for SCPSYS node representing the domain. 19 20properties: 21 $nodename: 22 pattern: '^power-controller(@[0-9a-f]+)?$' 23 24 compatible: 25 enum: 26 - mediatek,mt6735-power-controller 27 - mediatek,mt6795-power-controller 28 - mediatek,mt6893-power-controller 29 - mediatek,mt8167-power-controller 30 - mediatek,mt8173-power-controller 31 - mediatek,mt8183-power-controller 32 - mediatek,mt8186-power-controller 33 - mediatek,mt8188-power-controller 34 - mediatek,mt8192-power-controller 35 - mediatek,mt8195-power-controller 36 - mediatek,mt8365-power-controller 37 38 '#power-domain-cells': 39 const: 1 40 41 '#address-cells': 42 const: 1 43 44 '#size-cells': 45 const: 0 46 47 access-controllers: 48 description: 49 A number of phandles to external blocks to set and clear the required 50 bits to enable or disable bus protection, necessary to avoid any bus 51 faults while enabling or disabling a power domain. 52 For example, this may hold phandles to INFRACFG and SMI. 53 minItems: 1 54 maxItems: 3 55 56patternProperties: 57 "^power-domain@[0-9a-f]+$": 58 $ref: "#/$defs/power-domain-node" 59 patternProperties: 60 "^power-domain@[0-9a-f]+$": 61 $ref: "#/$defs/power-domain-node" 62 patternProperties: 63 "^power-domain@[0-9a-f]+$": 64 $ref: "#/$defs/power-domain-node" 65 patternProperties: 66 "^power-domain@[0-9a-f]+$": 67 $ref: "#/$defs/power-domain-node" 68 patternProperties: 69 "^power-domain@[0-9a-f]+$": 70 $ref: "#/$defs/power-domain-node" 71 unevaluatedProperties: false 72 unevaluatedProperties: false 73 unevaluatedProperties: false 74 unevaluatedProperties: false 75 unevaluatedProperties: false 76 77$defs: 78 power-domain-node: 79 type: object 80 description: | 81 Represents the power domains within the power controller node as documented 82 in Documentation/devicetree/bindings/power/power-domain.yaml. 83 84 properties: 85 86 '#power-domain-cells': 87 description: 88 Must be 0 for nodes representing a single PM domain and 1 for nodes 89 providing multiple PM domains. 90 91 '#address-cells': 92 const: 1 93 94 '#size-cells': 95 const: 0 96 97 reg: 98 description: | 99 Power domain index. Valid values are defined in: 100 "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. 101 "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. 102 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. 103 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. 104 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. 105 "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain. 106 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. 107 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. 108 "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain. 109 maxItems: 1 110 111 clocks: 112 description: | 113 A number of phandles to clocks that need to be enabled during domain 114 power-up sequencing. 115 116 clock-names: 117 description: | 118 List of names of clocks, in order to match the power-up sequencing 119 for each power domain we need to group the clocks by name. BASIC 120 clocks need to be enabled before enabling the corresponding power 121 domain, and should not have a '-' in their name (i.e mm, mfg, venc). 122 SUSBYS clocks need to be enabled before releasing the bus protection, 123 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). 124 125 In order to follow properly the power-up sequencing, the clocks must 126 be specified by order, adding first the BASIC clocks followed by the 127 SUSBSYS clocks. 128 129 domain-supply: 130 description: domain regulator supply. 131 132 mediatek,infracfg: 133 $ref: /schemas/types.yaml#/definitions/phandle 134 description: phandle to the device containing the INFRACFG register range. 135 deprecated: true 136 137 mediatek,infracfg-nao: 138 $ref: /schemas/types.yaml#/definitions/phandle 139 description: phandle to the device containing the INFRACFG-NAO register range. 140 deprecated: true 141 142 mediatek,smi: 143 $ref: /schemas/types.yaml#/definitions/phandle 144 description: phandle to the device containing the SMI register range. 145 deprecated: true 146 147 required: 148 - reg 149 150required: 151 - compatible 152 153allOf: 154 - if: 155 properties: 156 compatible: 157 contains: 158 enum: 159 - mediatek,mt8183-power-controller 160 then: 161 properties: 162 access-controllers: 163 minItems: 2 164 maxItems: 2 165 166 - if: 167 properties: 168 compatible: 169 contains: 170 enum: 171 - mediatek,mt8365-power-controller 172 then: 173 properties: 174 access-controllers: 175 minItems: 3 176 maxItems: 3 177 178additionalProperties: false 179 180examples: 181 - | 182 #include <dt-bindings/clock/mt8173-clk.h> 183 #include <dt-bindings/power/mt8173-power.h> 184 185 soc { 186 #address-cells = <2>; 187 #size-cells = <2>; 188 189 scpsys: syscon@10006000 { 190 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; 191 reg = <0 0x10006000 0 0x1000>; 192 193 spm: power-controller { 194 compatible = "mediatek,mt8173-power-controller"; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 #power-domain-cells = <1>; 198 199 /* power domains of the SoC */ 200 power-domain@MT8173_POWER_DOMAIN_VDEC { 201 reg = <MT8173_POWER_DOMAIN_VDEC>; 202 clocks = <&topckgen CLK_TOP_MM_SEL>; 203 clock-names = "mm"; 204 #power-domain-cells = <0>; 205 }; 206 power-domain@MT8173_POWER_DOMAIN_VENC { 207 reg = <MT8173_POWER_DOMAIN_VENC>; 208 clocks = <&topckgen CLK_TOP_MM_SEL>, 209 <&topckgen CLK_TOP_VENC_SEL>; 210 clock-names = "mm", "venc"; 211 #power-domain-cells = <0>; 212 }; 213 power-domain@MT8173_POWER_DOMAIN_ISP { 214 reg = <MT8173_POWER_DOMAIN_ISP>; 215 clocks = <&topckgen CLK_TOP_MM_SEL>; 216 clock-names = "mm"; 217 #power-domain-cells = <0>; 218 }; 219 power-domain@MT8173_POWER_DOMAIN_MM { 220 reg = <MT8173_POWER_DOMAIN_MM>; 221 clocks = <&topckgen CLK_TOP_MM_SEL>; 222 clock-names = "mm"; 223 #power-domain-cells = <0>; 224 mediatek,infracfg = <&infracfg>; 225 }; 226 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 227 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 228 clocks = <&topckgen CLK_TOP_MM_SEL>, 229 <&topckgen CLK_TOP_VENC_LT_SEL>; 230 clock-names = "mm", "venclt"; 231 #power-domain-cells = <0>; 232 }; 233 power-domain@MT8173_POWER_DOMAIN_AUDIO { 234 reg = <MT8173_POWER_DOMAIN_AUDIO>; 235 #power-domain-cells = <0>; 236 }; 237 power-domain@MT8173_POWER_DOMAIN_USB { 238 reg = <MT8173_POWER_DOMAIN_USB>; 239 #power-domain-cells = <0>; 240 }; 241 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 242 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 243 clocks = <&clk26m>; 244 clock-names = "mfg"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 #power-domain-cells = <1>; 248 249 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 250 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 #power-domain-cells = <1>; 254 255 power-domain@MT8173_POWER_DOMAIN_MFG { 256 reg = <MT8173_POWER_DOMAIN_MFG>; 257 #power-domain-cells = <0>; 258 mediatek,infracfg = <&infracfg>; 259 }; 260 }; 261 }; 262 }; 263 }; 264 }; 265