xref: /linux/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek MFlexGraphics Power and Frequency Controller
8
9maintainers:
10  - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
11
12description:
13  A special-purpose embedded MCU to control power and frequency of GPU devices
14  using MediaTek Flexible Graphics integration hardware.
15
16properties:
17  $nodename:
18    pattern: '^power-controller@[a-f0-9]+$'
19
20  compatible:
21    enum:
22      - mediatek,mt8196-gpufreq
23
24  reg:
25    items:
26      - description: GPR memory area
27      - description: RPC memory area
28      - description: SoC variant ID register
29
30  reg-names:
31    items:
32      - const: gpr
33      - const: rpc
34      - const: hw-revision
35
36  clocks:
37    items:
38      - description: main clock of the embedded controller (EB)
39      - description: core PLL
40      - description: stack 0 PLL
41      - description: stack 1 PLL
42
43  clock-names:
44    items:
45      - const: eb
46      - const: core
47      - const: stack0
48      - const: stack1
49
50  mboxes:
51    items:
52      - description: FastDVFS events
53      - description: frequency control
54      - description: sleep control
55      - description: timer control
56      - description: frequency hopping control
57      - description: hardware voter control
58      - description: FastDVFS control
59
60  mbox-names:
61    items:
62      - const: fast-dvfs-event
63      - const: gpufreq
64      - const: sleep
65      - const: timer
66      - const: fhctl
67      - const: ccf
68      - const: fast-dvfs
69
70  memory-region:
71    items:
72      - description: phandle to the GPUEB shared memory
73
74  "#clock-cells":
75    const: 1
76
77  "#nvmem-cell-cells":
78    const: 0
79
80  "#power-domain-cells":
81    const: 0
82
83  shader-present:
84    type: object
85
86dependencies:
87  shader-present: [ "#nvmem-cell-cells" ]
88
89required:
90  - compatible
91  - reg
92  - reg-names
93  - clocks
94  - clock-names
95  - mboxes
96  - mbox-names
97  - memory-region
98  - "#clock-cells"
99  - "#power-domain-cells"
100
101additionalProperties: false
102
103examples:
104  - |
105    #include <dt-bindings/clock/mediatek,mt8196-clock.h>
106
107    power-controller@4b09fd00 {
108        compatible = "mediatek,mt8196-gpufreq";
109        reg = <0x4b09fd00 0x80>,
110              <0x4b800000 0x1000>,
111              <0x4b860128 0x4>;
112        reg-names = "gpr", "rpc", "hw-revision";
113        clocks = <&topckgen CLK_TOP_MFG_EB>,
114                 <&mfgpll CLK_MFG_AO_MFGPLL>,
115                 <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>,
116                 <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>;
117        clock-names = "eb", "core", "stack0", "stack1";
118        mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>,
119                 <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>,
120                 <&gpueb_mbox 7>;
121        mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl",
122                     "ccf", "fast-dvfs";
123        memory-region = <&gpueb_shared_memory>;
124        #clock-cells = <1>;
125        #nvmem-cell-cells = <0>;
126        #power-domain-cells = <0>;
127
128        shader-present {
129        };
130    };
131