xref: /linux/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml (revision be1ca3ee8f97067fee87fda73ea5959d5ab75bbf) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX General Power Controller
8
9maintainers:
10  - Philipp Zabel <p.zabel@pengutronix.de>
11
12description: |
13  The i.MX6 General Power Control (GPC) block contains DVFS load tracking
14  counters and Power Gating Control (PGC).
15
16  The power domains are generic power domain providers as documented in
17  Documentation/devicetree/bindings/power/power-domain.yaml. They are
18  described as subnodes of the power gating controller 'pgc' node of the GPC.
19
20  IP cores belonging to a power domain should contain a 'power-domains'
21  property that is a phandle pointing to the power domain the device belongs
22  to.
23
24properties:
25  compatible:
26    oneOf:
27      - enum:
28          - fsl,imx6q-gpc
29      - items:
30          - enum:
31              - fsl,imx6qp-gpc
32              - fsl,imx6sl-gpc
33              - fsl,imx6sll-gpc
34              - fsl,imx6sx-gpc
35              - fsl,imx6ul-gpc
36          - const: fsl,imx6q-gpc
37
38  reg:
39    maxItems: 1
40
41  "#address-cells":
42    const: 0
43
44  interrupts:
45    maxItems: 1
46
47  interrupt-controller: true
48  '#interrupt-cells':
49    const: 3
50
51  clocks:
52    maxItems: 1
53
54  clock-names:
55    const: ipg
56
57  pgc:
58    type: object
59    additionalProperties: false
60    description: list of power domains provided by this controller.
61
62    properties:
63      '#address-cells':
64        const: 1
65
66      '#size-cells':
67        const: 0
68
69    patternProperties:
70      "power-domain@[0-9]$":
71        type: object
72        additionalProperties: false
73
74        properties:
75
76          '#power-domain-cells':
77            const: 0
78
79          reg:
80            description: |
81              The following DOMAIN_INDEX values are valid for i.MX6Q:
82                ARM_DOMAIN     0
83                PU_DOMAIN      1
84              The following additional DOMAIN_INDEX value is valid for i.MX6SL:
85                DISPLAY_DOMAIN 2
86              The following additional DOMAIN_INDEX value is valid for i.MX6SX:
87                PCI_DOMAIN     3
88            maxItems: 1
89
90          clocks:
91            description: |
92              A number of phandles to clocks that need to be enabled during domain
93              power-up sequencing to ensure reset propagation into devices located
94              inside this power domain.
95            minItems: 1
96            maxItems: 7
97
98          power-supply: true
99
100        required:
101          - '#power-domain-cells'
102          - reg
103
104    required:
105      - '#address-cells'
106      - '#size-cells'
107
108required:
109  - compatible
110  - reg
111  - interrupts
112  - clocks
113  - clock-names
114  - pgc
115
116additionalProperties: false
117
118examples:
119  - |
120    #include <dt-bindings/clock/imx6qdl-clock.h>
121    #include <dt-bindings/interrupt-controller/arm-gic.h>
122
123    gpc@20dc000 {
124        compatible = "fsl,imx6q-gpc";
125        reg = <0x020dc000 0x4000>;
126        interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
127        clocks = <&clks IMX6QDL_CLK_IPG>;
128        clock-names = "ipg";
129
130        pgc {
131            #address-cells = <1>;
132            #size-cells = <0>;
133
134            power-domain@0 {
135                reg = <0>;
136                #power-domain-cells = <0>;
137            };
138
139            pd_pu: power-domain@1 {
140                reg = <1>;
141                #power-domain-cells = <0>;
142                power-supply = <&reg_pu>;
143                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
144                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
145                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
146                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
147                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
148                         <&clks IMX6QDL_CLK_VPU_AXI>;
149            };
150        };
151    };
152