xref: /linux/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX General Power Controller
8
9maintainers:
10  - Philipp Zabel <p.zabel@pengutronix.de>
11
12description: |
13  The i.MX6 General Power Control (GPC) block contains DVFS load tracking
14  counters and Power Gating Control (PGC).
15
16  The power domains are generic power domain providers as documented in
17  Documentation/devicetree/bindings/power/power-domain.yaml. They are
18  described as subnodes of the power gating controller 'pgc' node of the GPC.
19
20  IP cores belonging to a power domain should contain a 'power-domains'
21  property that is a phandle pointing to the power domain the device belongs
22  to.
23
24properties:
25  compatible:
26    oneOf:
27      - enum:
28          - fsl,imx6q-gpc
29      - items:
30          - enum:
31              - fsl,imx6qp-gpc
32              - fsl,imx6sl-gpc
33              - fsl,imx6sll-gpc
34              - fsl,imx6sx-gpc
35              - fsl,imx6ul-gpc
36          - const: fsl,imx6q-gpc
37
38  reg:
39    maxItems: 1
40
41  interrupts:
42    maxItems: 1
43
44  interrupt-controller: true
45  '#interrupt-cells':
46    const: 3
47
48  clocks:
49    maxItems: 1
50
51  clock-names:
52    const: ipg
53
54  pgc:
55    type: object
56    additionalProperties: false
57    description: list of power domains provided by this controller.
58
59    properties:
60      '#address-cells':
61        const: 1
62
63      '#size-cells':
64        const: 0
65
66    patternProperties:
67      "power-domain@[0-9]$":
68        type: object
69        additionalProperties: false
70
71        properties:
72
73          '#power-domain-cells':
74            const: 0
75
76          reg:
77            description: |
78              The following DOMAIN_INDEX values are valid for i.MX6Q:
79                ARM_DOMAIN     0
80                PU_DOMAIN      1
81              The following additional DOMAIN_INDEX value is valid for i.MX6SL:
82                DISPLAY_DOMAIN 2
83              The following additional DOMAIN_INDEX value is valid for i.MX6SX:
84                PCI_DOMAIN     3
85            maxItems: 1
86
87          clocks:
88            description: |
89              A number of phandles to clocks that need to be enabled during domain
90              power-up sequencing to ensure reset propagation into devices located
91              inside this power domain.
92            minItems: 1
93            maxItems: 7
94
95          power-supply: true
96
97        required:
98          - '#power-domain-cells'
99          - reg
100
101    required:
102      - '#address-cells'
103      - '#size-cells'
104
105required:
106  - compatible
107  - reg
108  - interrupts
109  - clocks
110  - clock-names
111  - pgc
112
113additionalProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/clock/imx6qdl-clock.h>
118    #include <dt-bindings/interrupt-controller/arm-gic.h>
119
120    gpc@20dc000 {
121        compatible = "fsl,imx6q-gpc";
122        reg = <0x020dc000 0x4000>;
123        interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
124        clocks = <&clks IMX6QDL_CLK_IPG>;
125        clock-names = "ipg";
126
127        pgc {
128            #address-cells = <1>;
129            #size-cells = <0>;
130
131            power-domain@0 {
132                reg = <0>;
133                #power-domain-cells = <0>;
134            };
135
136            pd_pu: power-domain@1 {
137                reg = <1>;
138                #power-domain-cells = <0>;
139                power-supply = <&reg_pu>;
140                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
141                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
142                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
143                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
144                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
145                         <&clks IMX6QDL_CLK_VPU_AXI>;
146            };
147        };
148    };
149