xref: /linux/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml (revision 7b3c2046f6fc97324c58904b56f9e7a2c0f27049)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX General Power Controller

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  The i.MX6 General Power Control (GPC) block contains DVFS load tracking
  counters and Power Gating Control (PGC).

  The power domains are generic power domain providers as documented in
  Documentation/devicetree/bindings/power/power-domain.yaml. They are
  described as subnodes of the power gating controller 'pgc' node of the GPC.

  IP cores belonging to a power domain should contain a 'power-domains'
  property that is a phandle pointing to the power domain the device belongs
  to.

properties:
  compatible:
    enum:
      - fsl,imx6q-gpc
      - fsl,imx6qp-gpc
      - fsl,imx6sl-gpc
      - fsl,imx6sx-gpc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: ipg

  pgc:
    type: object
    additionalProperties: false
    description: list of power domains provided by this controller.

    properties:
      '#address-cells':
        const: 1

      '#size-cells':
        const: 0

    patternProperties:
      "power-domain@[0-9]$":
        type: object
        additionalProperties: false

        properties:

          '#power-domain-cells':
            const: 0

          reg:
            description: |
              The following DOMAIN_INDEX values are valid for i.MX6Q:
                ARM_DOMAIN     0
                PU_DOMAIN      1
              The following additional DOMAIN_INDEX value is valid for i.MX6SL:
                DISPLAY_DOMAIN 2
              The following additional DOMAIN_INDEX value is valid for i.MX6SX:
                PCI_DOMAIN     3
            maxItems: 1

          clocks:
            description: |
              A number of phandles to clocks that need to be enabled during domain
              power-up sequencing to ensure reset propagation into devices located
              inside this power domain.
            minItems: 1
            maxItems: 7

          power-supply: true

        required:
          - '#power-domain-cells'
          - reg

    required:
      - '#address-cells'
      - '#size-cells'

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - pgc

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpc@20dc000 {
        compatible = "fsl,imx6q-gpc";
        reg = <0x020dc000 0x4000>;
        interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_IPG>;
        clock-names = "ipg";

        pgc {
            #address-cells = <1>;
            #size-cells = <0>;

            power-domain@0 {
                reg = <0>;
                #power-domain-cells = <0>;
            };

            pd_pu: power-domain@1 {
                reg = <1>;
                #power-domain-cells = <0>;
                power-supply = <&reg_pu>;
                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
                         <&clks IMX6QDL_CLK_VPU_AXI>;
            };
        };
    };