1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: T-Head TH1520 SoC pin controller 8 9maintainers: 10 - Emil Renner Berthing <emil.renner.berthing@canonical.com> 11 12description: | 13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. 14 15 The TH1520 has 3 groups of pads each controlled from different memory ranges. 16 Confusingly the memory ranges are named 17 PADCTRL_AOSYS -> PAD Group 1 18 PADCTRL1_APSYS -> PAD Group 2 19 PADCTRL0_APSYS -> PAD Group 3 20 21 Each pad can be muxed individually to up to 6 different functions. For most 22 pads only a few of those 6 configurations are valid though, and a few pads in 23 group 1 does not support muxing at all. 24 25 Pinconf is fairly regular except for a few pads in group 1 that either can't 26 be configured or has some special functions. The rest have configurable drive 27 strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in 28 addition to a special strong pull up. 29 30 Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and 31 are then meant to be used by the audio co-processor. Each such pad can then 32 be further muxed to either audio GPIO or one of 4 functions such as UART, I2C 33 and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is 34 also configured in different registers. All of this is done from a different 35 AUDIO_IOCTRL memory range and is left to the audio co-processor for now. 36 37properties: 38 compatible: 39 enum: 40 - thead,th1520-pinctrl 41 reg: 42 maxItems: 1 43 44 clocks: 45 maxItems: 1 46 47 thead,pad-group: 48 description: | 49 Select the pad group that is associated with the pin controller instance. 50 51 Base Address Name Group 52 0xFF_FFF4_A000 PADCTRL_AOSYS 1 53 0xFF_E7F3_C000 PADCTRL1_APSYS 2 54 0xFF_EC00_7000 PADCTRL0_APSYS 3 55 56 $ref: /schemas/types.yaml#/definitions/uint32 57 enum: [1, 2, 3] 58 59required: 60 - compatible 61 - reg 62 - clocks 63 64patternProperties: 65 '-[0-9]+$': 66 type: object 67 additionalProperties: false 68 69 patternProperties: 70 '-pins$': 71 type: object 72 allOf: 73 - $ref: /schemas/pinctrl/pincfg-node.yaml# 74 - $ref: /schemas/pinctrl/pinmux-node.yaml# 75 76 additionalProperties: false 77 78 description: 79 A pinctrl node should contain at least one subnode describing one 80 or more pads and their associated pinmux and pinconf settings. 81 82 properties: 83 pins: 84 description: List of pads that properties in the node apply to. 85 86 function: 87 enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, 88 gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, 89 clock, jtag, iso7816, efuse, reset ] 90 description: The mux function to select for the given pins. 91 92 bias-disable: true 93 94 bias-pull-up: 95 oneOf: 96 - type: boolean 97 description: Enable the regular 48kOhm pull-up 98 - enum: [ 2100, 48000 ] 99 description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up 100 101 bias-pull-down: 102 oneOf: 103 - type: boolean 104 - const: 44000 105 description: Enable the regular 44kOhm pull-down 106 107 drive-strength: 108 enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ] 109 description: Drive strength in mA 110 111 input-enable: true 112 113 input-disable: true 114 115 input-schmitt-enable: true 116 117 input-schmitt-disable: true 118 119 slew-rate: 120 maximum: 1 121 122 required: 123 - pins 124 125additionalProperties: false 126 127examples: 128 - | 129 padctrl0_apsys: pinctrl@ec007000 { 130 compatible = "thead,th1520-pinctrl"; 131 reg = <0xec007000 0x1000>; 132 clocks = <&apb_clk>; 133 thead,pad-group = <3>; 134 135 uart0_pins: uart0-0 { 136 tx-pins { 137 pins = "UART0_TXD"; 138 function = "uart"; 139 bias-disable; 140 drive-strength = <3>; 141 input-disable; 142 input-schmitt-disable; 143 slew-rate = <0>; 144 }; 145 146 rx-pins { 147 pins = "UART0_RXD"; 148 function = "uart"; 149 bias-disable; 150 drive-strength = <1>; 151 input-enable; 152 input-schmitt-enable; 153 slew-rate = <0>; 154 }; 155 }; 156 }; 157 158 padctrl1_apsys: pinctrl@e7f3c000 { 159 compatible = "thead,th1520-pinctrl"; 160 reg = <0xe7f3c000 0x1000>; 161 clocks = <&apb_clk>; 162 thead,pad-group = <2>; 163 164 i2c5_pins: i2c5-0 { 165 i2c-pins { 166 pins = "QSPI1_CSN0", /* I2C5_SCL */ 167 "QSPI1_D0_MOSI"; /* I2C5_SDA */ 168 function = "i2c"; 169 bias-pull-up = <2100>; 170 drive-strength = <7>; 171 input-enable; 172 input-schmitt-enable; 173 slew-rate = <0>; 174 }; 175 }; 176 }; 177