1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2# Copyright (C) STMicroelectronics 2019. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: STM32 GPIO and Pin Mux/Config controller 9 10maintainers: 11 - Alexandre TORGUE <alexandre.torgue@foss.st.com> 12 13description: | 14 STMicroelectronics's STM32 MCUs integrate a GPIO and Pin mux/config hardware 15 controller. It controls the input/output settings on the available pins and 16 also provides ability to multiplex and configure the output of various 17 on-chip controllers onto these pads. 18 19properties: 20 compatible: 21 enum: 22 - st,stm32f429-pinctrl 23 - st,stm32f469-pinctrl 24 - st,stm32f746-pinctrl 25 - st,stm32f769-pinctrl 26 - st,stm32h743-pinctrl 27 - st,stm32mp135-pinctrl 28 - st,stm32mp157-pinctrl 29 - st,stm32mp157-z-pinctrl 30 - st,stm32mp257-pinctrl 31 - st,stm32mp257-z-pinctrl 32 33 '#address-cells': 34 const: 1 35 36 '#size-cells': 37 const: 1 38 39 ranges: true 40 41 pins-are-numbered: 42 $ref: /schemas/types.yaml#/definitions/flag 43 deprecated: true 44 45 hwlocks: true 46 47 interrupts: 48 maxItems: 1 49 50 st,syscfg: 51 description: Phandle+args to the syscon node which includes IRQ mux selection. 52 $ref: /schemas/types.yaml#/definitions/phandle-array 53 items: 54 - minItems: 2 55 items: 56 - description: syscon node which includes IRQ mux selection 57 - description: The offset of the IRQ mux selection register 58 - description: The field mask of IRQ mux, needed if different of 0xf 59 60 st,package: 61 description: 62 Indicates the SOC package used. 63 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h 64 $ref: /schemas/types.yaml#/definitions/uint32 65 enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800] 66 67patternProperties: 68 '^gpio@[0-9a-f]*$': 69 type: object 70 additionalProperties: false 71 properties: 72 gpio-controller: true 73 74 '#gpio-cells': 75 const: 2 76 77 interrupt-controller: true 78 '#interrupt-cells': 79 const: 2 80 81 reg: 82 maxItems: 1 83 84 clocks: 85 maxItems: 1 86 87 resets: 88 maxItems: 1 89 90 gpio-line-names: true 91 92 gpio-ranges: 93 minItems: 1 94 maxItems: 16 95 96 ngpios: 97 description: 98 Number of available gpios in a bank. 99 minimum: 1 100 maximum: 16 101 102 st,bank-name: 103 description: 104 Should be a name string for this bank as specified in the datasheet. 105 $ref: /schemas/types.yaml#/definitions/string 106 enum: 107 - GPIOA 108 - GPIOB 109 - GPIOC 110 - GPIOD 111 - GPIOE 112 - GPIOF 113 - GPIOG 114 - GPIOH 115 - GPIOI 116 - GPIOJ 117 - GPIOK 118 - GPIOZ 119 120 st,bank-ioport: 121 description: 122 Should correspond to the EXTI IOport selection (EXTI line used 123 to select GPIOs as interrupts). 124 $ref: /schemas/types.yaml#/definitions/uint32 125 minimum: 0 126 maximum: 11 127 128 patternProperties: 129 "^(.+-hog(-[0-9]+)?)$": 130 type: object 131 required: 132 - gpio-hog 133 134 required: 135 - gpio-controller 136 - '#gpio-cells' 137 - reg 138 - clocks 139 - st,bank-name 140 141 '-[0-9]*$': 142 type: object 143 additionalProperties: false 144 145 patternProperties: 146 '^pins': 147 type: object 148 additionalProperties: false 149 description: | 150 A pinctrl node should contain at least one subnode representing the 151 pinctrl group available on the machine. Each subnode will list the 152 pins it needs, and how they should be configured, with regard to muxer 153 configuration, pullups, drive, output high/low and output speed. 154 properties: 155 pinmux: 156 $ref: /schemas/types.yaml#/definitions/uint32-array 157 description: | 158 Integer array, represents gpio pin number and mux setting. 159 Supported pin number and mux varies for different SoCs, and are 160 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly. 161 These defines are calculated as: ((port * 16 + line) << 8) | function 162 With: 163 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) 164 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) 165 - function: The function number, can be: 166 * 0 : GPIO 167 * 1 : Alternate Function 0 168 * 2 : Alternate Function 1 169 * 3 : Alternate Function 2 170 * ... 171 * 16 : Alternate Function 15 172 * 17 : Analog 173 * 18 : Reserved 174 To simplify the usage, macro is available to generate "pinmux" field. 175 This macro is available here: 176 - include/dt-bindings/pinctrl/stm32-pinfunc.h 177 Setting the pinmux's function to the Reserved (RSVD) value is used to inform 178 the driver that it shall not apply the mux setting. This can be used to 179 reserve some pins, for example to a co-processor not running Linux. 180 Some examples of using macro: 181 /* GPIO A9 set as alternate function 2 */ 182 ... { 183 pinmux = <STM32_PINMUX('A', 9, AF2)>; 184 }; 185 /* GPIO A9 set as GPIO */ 186 ... { 187 pinmux = <STM32_PINMUX('A', 9, GPIO)>; 188 }; 189 /* GPIO A9 set as analog */ 190 ... { 191 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; 192 }; 193 /* GPIO A9 reserved for co-processor */ 194 ... { 195 pinmux = <STM32_PINMUX('A', 9, RSVD)>; 196 }; 197 198 bias-disable: 199 type: boolean 200 201 bias-pull-down: 202 type: boolean 203 204 bias-pull-up: 205 type: boolean 206 207 drive-push-pull: 208 type: boolean 209 210 drive-open-drain: 211 type: boolean 212 213 output-low: 214 type: boolean 215 216 output-high: 217 type: boolean 218 219 slew-rate: 220 description: | 221 0: Low speed 222 1: Medium speed 223 2: Fast speed 224 3: High speed 225 $ref: /schemas/types.yaml#/definitions/uint32 226 enum: [0, 1, 2, 3] 227 228 required: 229 - pinmux 230 231allOf: 232 - $ref: pinctrl.yaml# 233 234required: 235 - compatible 236 - '#address-cells' 237 - '#size-cells' 238 - ranges 239 240additionalProperties: false 241 242examples: 243 - | 244 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 245 #include <dt-bindings/mfd/stm32f4-rcc.h> 246 //Example 1 247 pinctrl@40020000 { 248 #address-cells = <1>; 249 #size-cells = <1>; 250 compatible = "st,stm32f429-pinctrl"; 251 ranges = <0 0x40020000 0x3000>; 252 253 gpioa: gpio@0 { 254 gpio-controller; 255 #gpio-cells = <2>; 256 reg = <0x0 0x400>; 257 resets = <&reset_ahb1 0>; 258 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; 259 st,bank-name = "GPIOA"; 260 }; 261 }; 262 263 //Example 2 (using gpio-ranges) 264 pinctrl@50020000 { 265 #address-cells = <1>; 266 #size-cells = <1>; 267 compatible = "st,stm32f429-pinctrl"; 268 ranges = <0 0x50020000 0x3000>; 269 270 gpiob: gpio@1000 { 271 gpio-controller; 272 #gpio-cells = <2>; 273 reg = <0x1000 0x400>; 274 resets = <&reset_ahb1 0>; 275 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; 276 st,bank-name = "GPIOB"; 277 gpio-ranges = <&pinctrl 0 0 16>; 278 }; 279 280 gpioc: gpio@2000 { 281 gpio-controller; 282 #gpio-cells = <2>; 283 reg = <0x2000 0x400>; 284 resets = <&reset_ahb1 0>; 285 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; 286 st,bank-name = "GPIOC"; 287 ngpios = <5>; 288 gpio-ranges = <&pinctrl 0 16 3>, 289 <&pinctrl 14 30 2>; 290 }; 291 }; 292 293 //Example 3 pin groups 294 pinctrl { 295 usart1_pins_a: usart1-0 { 296 pins1 { 297 pinmux = <STM32_PINMUX('A', 9, AF7)>; 298 bias-disable; 299 drive-push-pull; 300 slew-rate = <0>; 301 }; 302 pins2 { 303 pinmux = <STM32_PINMUX('A', 10, AF7)>; 304 bias-disable; 305 }; 306 }; 307 }; 308 309 usart1 { 310 pinctrl-0 = <&usart1_pins_a>; 311 pinctrl-names = "default"; 312 }; 313 314... 315