1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung S3C/S5P/Exynos SoC pin controller 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Sylwester Nawrocki <s.nawrocki@samsung.com> 12 - Tomasz Figa <tomasz.figa@gmail.com> 13 14description: | 15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 16 controller. 17 18 All the pin controller nodes should be represented in the aliases node using 19 the following format 'pinctrl{n}' where n is a unique number for the alias. 20 21 The controller supports three types of interrupts:: 22 - External GPIO interrupts (see interrupts property in pin controller node); 23 24 - External wake-up interrupts - multiplexed (capable of waking up the system 25 see interrupts property in external wake-up interrupt controller node - 26 samsung,pinctrl-wakeup-interrupt.yaml); 27 28 - External wake-up interrupts - direct (capable of waking up the system, see 29 interrupts property in every bank of pin controller with external wake-up 30 interrupt controller - samsung,pinctrl-gpio-bank.yaml). 31 32properties: 33 $nodename: 34 pattern: "^pinctrl(@.*)?" 35 36 compatible: 37 enum: 38 - axis,artpec8-pinctrl 39 - axis,artpec9-pinctrl 40 - google,gs101-pinctrl 41 - samsung,s3c64xx-pinctrl 42 - samsung,s5pv210-pinctrl 43 - samsung,exynos2200-pinctrl 44 - samsung,exynos3250-pinctrl 45 - samsung,exynos4210-pinctrl 46 - samsung,exynos4x12-pinctrl 47 - samsung,exynos5250-pinctrl 48 - samsung,exynos5260-pinctrl 49 - samsung,exynos5410-pinctrl 50 - samsung,exynos5420-pinctrl 51 - samsung,exynos5433-pinctrl 52 - samsung,exynos7-pinctrl 53 - samsung,exynos7870-pinctrl 54 - samsung,exynos7885-pinctrl 55 - samsung,exynos850-pinctrl 56 - samsung,exynos8890-pinctrl 57 - samsung,exynos8895-pinctrl 58 - samsung,exynos9810-pinctrl 59 - samsung,exynos990-pinctrl 60 - samsung,exynosautov9-pinctrl 61 - samsung,exynosautov920-pinctrl 62 - tesla,fsd-pinctrl 63 64 interrupts: 65 description: 66 Required for GPIO banks supporting external GPIO interrupts. 67 maxItems: 1 68 69 power-domains: 70 maxItems: 1 71 72 reg: 73 description: 74 Second base address of the pin controller if the specific registers of 75 the pin controller are separated into the different base address. 76 Only certain banks of certain pin controller might need it. 77 minItems: 1 78 maxItems: 2 79 80 clocks: 81 maxItems: 1 82 83 clock-names: 84 items: 85 - const: pclk 86 87 wakeup-interrupt-controller: 88 $ref: samsung,pinctrl-wakeup-interrupt.yaml 89 90patternProperties: 91 "^[a-z]+[0-9]*-gpio-bank$": 92 description: 93 Pin banks of the controller are represented by child nodes of the 94 controller node. Bank name is taken from name of the node. 95 $ref: samsung,pinctrl-gpio-bank.yaml 96 97 "^[a-z0-9-]+-pins$": 98 oneOf: 99 - $ref: samsung,pinctrl-pins-cfg.yaml 100 required: 101 - samsung,pins 102 - type: object 103 patternProperties: 104 "^[a-z0-9-]+-pins$": 105 $ref: samsung,pinctrl-pins-cfg.yaml 106 107 additionalProperties: false 108 109 "^(initial|sleep)-state$": 110 type: object 111 additionalProperties: false 112 113 patternProperties: 114 "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$": 115 $ref: samsung,pinctrl-pins-cfg.yaml 116 117 properties: 118 samsung,pins: 119 description: See samsung,pinctrl-pins-cfg.yaml 120 $ref: /schemas/types.yaml#/definitions/string-array 121 maxItems: 1 122 123 required: 124 - samsung,pins 125 126 unevaluatedProperties: false 127 128required: 129 - compatible 130 - reg 131 132allOf: 133 - $ref: pinctrl.yaml# 134 - if: 135 properties: 136 compatible: 137 contains: 138 enum: 139 - google,gs101-pinctrl 140 - samsung,exynos8890-pinctrl 141 then: 142 required: 143 - clocks 144 - clock-names 145 else: 146 properties: 147 clocks: false 148 clock-names: false 149 150 - if: 151 properties: 152 compatible: 153 contains: 154 const: samsung,exynos5433-pinctrl 155 then: 156 properties: 157 reg: 158 minItems: 1 159 maxItems: 2 160 else: 161 properties: 162 reg: 163 minItems: 1 164 maxItems: 1 165 166additionalProperties: false 167 168examples: 169 - | 170 pinctrl@7f008000 { 171 compatible = "samsung,s3c64xx-pinctrl"; 172 reg = <0x7f008000 0x1000>; 173 interrupt-parent = <&vic1>; 174 interrupts = <21>; 175 176 wakeup-interrupt-controller { 177 compatible = "samsung,s3c64xx-wakeup-eint"; 178 interrupts-extended = <&vic0 0>, 179 <&vic0 1>, 180 <&vic1 0>, 181 <&vic1 1>; 182 }; 183 184 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 185 gpa-gpio-bank { 186 gpio-controller; 187 #gpio-cells = <2>; 188 interrupt-controller; 189 #interrupt-cells = <2>; 190 }; 191 192 // ... 193 194 uart0-data-pins { 195 samsung,pins = "gpa-0", "gpa-1"; 196 samsung,pin-function = <2>; 197 samsung,pin-pud = <0>; 198 }; 199 200 // ... 201 }; 202 203 - | 204 #include <dt-bindings/interrupt-controller/arm-gic.h> 205 206 pinctrl@11400000 { 207 compatible = "samsung,exynos4210-pinctrl"; 208 reg = <0x11400000 0x1000>; 209 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 210 211 pinctrl-names = "default"; 212 pinctrl-0 = <&sleep0>; 213 214 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 215 gpa0-gpio-bank { 216 gpio-controller; 217 #gpio-cells = <2>; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 }; 221 222 // ... 223 224 uart0-data-pins { 225 samsung,pins = "gpa0-0", "gpa0-1"; 226 samsung,pin-function = <2>; 227 samsung,pin-pud = <0>; 228 samsung,pin-drv = <0>; 229 }; 230 231 // ... 232 233 sleep0: sleep-state { 234 gpa0-0-pin { 235 samsung,pins = "gpa0-0"; 236 samsung,pin-con-pdn = <2>; 237 samsung,pin-pud-pdn = <0>; 238 }; 239 240 gpa0-1-pin { 241 samsung,pins = "gpa0-1"; 242 samsung,pin-con-pdn = <0>; 243 samsung,pin-pud-pdn = <0>; 244 }; 245 246 // ... 247 }; 248 }; 249 250 - | 251 #include <dt-bindings/interrupt-controller/arm-gic.h> 252 253 pinctrl@11000000 { 254 compatible = "samsung,exynos4210-pinctrl"; 255 reg = <0x11000000 0x1000>; 256 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 257 258 wakeup-interrupt-controller { 259 compatible = "samsung,exynos4210-wakeup-eint"; 260 interrupt-parent = <&gic>; 261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 264 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 265 gpj0-gpio-bank { 266 gpio-controller; 267 #gpio-cells = <2>; 268 interrupt-controller; 269 #interrupt-cells = <2>; 270 }; 271 272 /* Pin bank without external interrupts */ 273 gpy0-gpio-bank { 274 gpio-controller; 275 #gpio-cells = <2>; 276 }; 277 278 /* Pin bank with external direct wake-up interrupts */ 279 gpx0-gpio-bank { 280 gpio-controller; 281 #gpio-cells = <2>; 282 283 interrupt-controller; 284 interrupt-parent = <&gic>; 285 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 293 #interrupt-cells = <2>; 294 }; 295 296 // ... 297 298 sd0-clk-pins { 299 samsung,pins = "gpk0-0"; 300 samsung,pin-function = <2>; 301 samsung,pin-pud = <0>; 302 samsung,pin-drv = <3>; 303 }; 304 305 sd4-bus-width8-pins { 306 part-1-pins { 307 samsung,pins = "gpk0-3", "gpk0-4", 308 "gpk0-5", "gpk0-6"; 309 samsung,pin-function = <3>; 310 samsung,pin-pud = <3>; 311 samsung,pin-drv = <3>; 312 }; 313 314 part-2-pins { 315 samsung,pins = "gpk1-3", "gpk1-4", 316 "gpk1-5", "gpk1-6"; 317 samsung,pin-function = <4>; 318 samsung,pin-pud = <3>; 319 samsung,pin-drv = <3>; 320 }; 321 }; 322 323 // ... 324 325 otg-gp-pins { 326 samsung,pins = "gpx3-3"; 327 samsung,pin-function = <1>; 328 samsung,pin-pud = <0>; 329 samsung,pin-drv = <0>; 330 samsung,pin-val = <0>; 331 }; 332 }; 333 334 - | 335 #include <dt-bindings/interrupt-controller/arm-gic.h> 336 337 pinctrl@10580000 { 338 compatible = "samsung,exynos5433-pinctrl"; 339 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 340 341 pinctrl-names = "default"; 342 pinctrl-0 = <&initial_alive>; 343 344 wakeup-interrupt-controller { 345 compatible = "samsung,exynos5433-wakeup-eint", 346 "samsung,exynos7-wakeup-eint"; 347 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 348 }; 349 350 /* Pin bank with external direct wake-up interrupts */ 351 gpa0-gpio-bank { 352 gpio-controller; 353 #gpio-cells = <2>; 354 355 interrupt-controller; 356 interrupt-parent = <&gic>; 357 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 365 #interrupt-cells = <2>; 366 }; 367 368 // ... 369 370 te-irq-pins { 371 samsung,pins = "gpf1-3"; 372 samsung,pin-function = <0xf>; 373 }; 374 375 // .. 376 377 initial_alive: initial-state { 378 gpa0-0-pin { 379 samsung,pins = "gpa0-0"; 380 samsung,pin-function = <0>; 381 samsung,pin-pud = <1>; 382 samsung,pin-drv = <0>; 383 }; 384 385 // ... 386 }; 387 }; 388 389 - | 390 #include <dt-bindings/interrupt-controller/arm-gic.h> 391 392 pinctrl@114b0000 { 393 compatible = "samsung,exynos5433-pinctrl"; 394 reg = <0x114b0000 0x1000>; 395 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 396 power-domains = <&pd_aud>; 397 398 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 399 gpz0-gpio-bank { 400 gpio-controller; 401 #gpio-cells = <2>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 }; 405 406 // ... 407 408 i2s0-bus-pins { 409 samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", 410 "gpz0-4", "gpz0-5", "gpz0-6"; 411 samsung,pin-function = <2>; 412 samsung,pin-pud = <0>; 413 samsung,pin-drv = <0>; 414 }; 415 416 // ... 417 }; 418