1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Samsung S3C/S5P/Exynos SoC pin controller 8 9maintainers: 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Sylwester Nawrocki <s.nawrocki@samsung.com> 12 - Tomasz Figa <tomasz.figa@gmail.com> 13 14description: | 15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 16 controller. 17 18 All the pin controller nodes should be represented in the aliases node using 19 the following format 'pinctrl{n}' where n is a unique number for the alias. 20 21 The controller supports three types of interrupts:: 22 - External GPIO interrupts (see interrupts property in pin controller node); 23 24 - External wake-up interrupts - multiplexed (capable of waking up the system 25 see interrupts property in external wake-up interrupt controller node - 26 samsung,pinctrl-wakeup-interrupt.yaml); 27 28 - External wake-up interrupts - direct (capable of waking up the system, see 29 interrupts property in every bank of pin controller with external wake-up 30 interrupt controller - samsung,pinctrl-gpio-bank.yaml). 31 32properties: 33 $nodename: 34 pattern: "^pinctrl(@.*)?" 35 36 compatible: 37 enum: 38 - google,gs101-pinctrl 39 - samsung,s3c2412-pinctrl 40 - samsung,s3c2416-pinctrl 41 - samsung,s3c2440-pinctrl 42 - samsung,s3c2450-pinctrl 43 - samsung,s3c64xx-pinctrl 44 - samsung,s5pv210-pinctrl 45 - samsung,exynos3250-pinctrl 46 - samsung,exynos4210-pinctrl 47 - samsung,exynos4x12-pinctrl 48 - samsung,exynos5250-pinctrl 49 - samsung,exynos5260-pinctrl 50 - samsung,exynos5410-pinctrl 51 - samsung,exynos5420-pinctrl 52 - samsung,exynos5433-pinctrl 53 - samsung,exynos7-pinctrl 54 - samsung,exynos7885-pinctrl 55 - samsung,exynos850-pinctrl 56 - samsung,exynos8895-pinctrl 57 - samsung,exynos9810-pinctrl 58 - samsung,exynos990-pinctrl 59 - samsung,exynosautov9-pinctrl 60 - samsung,exynosautov920-pinctrl 61 - tesla,fsd-pinctrl 62 63 interrupts: 64 description: 65 Required for GPIO banks supporting external GPIO interrupts. 66 maxItems: 1 67 68 power-domains: 69 maxItems: 1 70 71 reg: 72 description: 73 Second base address of the pin controller if the specific registers of 74 the pin controller are separated into the different base address. 75 Only certain banks of certain pin controller might need it. 76 minItems: 1 77 maxItems: 2 78 79 clocks: 80 maxItems: 1 81 82 clock-names: 83 items: 84 - const: pclk 85 86 wakeup-interrupt-controller: 87 $ref: samsung,pinctrl-wakeup-interrupt.yaml 88 89patternProperties: 90 "^[a-z]+[0-9]*-gpio-bank$": 91 description: 92 Pin banks of the controller are represented by child nodes of the 93 controller node. Bank name is taken from name of the node. 94 $ref: samsung,pinctrl-gpio-bank.yaml 95 96 "^[a-z0-9-]+-pins$": 97 oneOf: 98 - $ref: samsung,pinctrl-pins-cfg.yaml 99 required: 100 - samsung,pins 101 - type: object 102 patternProperties: 103 "^[a-z0-9-]+-pins$": 104 $ref: samsung,pinctrl-pins-cfg.yaml 105 106 additionalProperties: false 107 108 "^(initial|sleep)-state$": 109 type: object 110 additionalProperties: false 111 112 patternProperties: 113 "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$": 114 $ref: samsung,pinctrl-pins-cfg.yaml 115 116 properties: 117 samsung,pins: 118 description: See samsung,pinctrl-pins-cfg.yaml 119 $ref: /schemas/types.yaml#/definitions/string-array 120 maxItems: 1 121 122 required: 123 - samsung,pins 124 125 unevaluatedProperties: false 126 127required: 128 - compatible 129 - reg 130 131allOf: 132 - $ref: pinctrl.yaml# 133 - if: 134 properties: 135 compatible: 136 contains: 137 const: google,gs101-pinctrl 138 then: 139 required: 140 - clocks 141 - clock-names 142 else: 143 properties: 144 clocks: false 145 clock-names: false 146 147 - if: 148 properties: 149 compatible: 150 contains: 151 const: samsung,exynos5433-pinctrl 152 then: 153 properties: 154 reg: 155 minItems: 1 156 maxItems: 2 157 else: 158 properties: 159 reg: 160 minItems: 1 161 maxItems: 1 162 163additionalProperties: false 164 165examples: 166 - | 167 pinctrl@7f008000 { 168 compatible = "samsung,s3c64xx-pinctrl"; 169 reg = <0x7f008000 0x1000>; 170 interrupt-parent = <&vic1>; 171 interrupts = <21>; 172 173 wakeup-interrupt-controller { 174 compatible = "samsung,s3c64xx-wakeup-eint"; 175 interrupts-extended = <&vic0 0>, 176 <&vic0 1>, 177 <&vic1 0>, 178 <&vic1 1>; 179 }; 180 181 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 182 gpa-gpio-bank { 183 gpio-controller; 184 #gpio-cells = <2>; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 }; 188 189 // ... 190 191 uart0-data-pins { 192 samsung,pins = "gpa-0", "gpa-1"; 193 samsung,pin-function = <2>; 194 samsung,pin-pud = <0>; 195 }; 196 197 // ... 198 }; 199 200 - | 201 #include <dt-bindings/interrupt-controller/arm-gic.h> 202 203 pinctrl@11400000 { 204 compatible = "samsung,exynos4210-pinctrl"; 205 reg = <0x11400000 0x1000>; 206 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 207 208 pinctrl-names = "default"; 209 pinctrl-0 = <&sleep0>; 210 211 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 212 gpa0-gpio-bank { 213 gpio-controller; 214 #gpio-cells = <2>; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 }; 218 219 // ... 220 221 uart0-data-pins { 222 samsung,pins = "gpa0-0", "gpa0-1"; 223 samsung,pin-function = <2>; 224 samsung,pin-pud = <0>; 225 samsung,pin-drv = <0>; 226 }; 227 228 // ... 229 230 sleep0: sleep-state { 231 gpa0-0-pin { 232 samsung,pins = "gpa0-0"; 233 samsung,pin-con-pdn = <2>; 234 samsung,pin-pud-pdn = <0>; 235 }; 236 237 gpa0-1-pin { 238 samsung,pins = "gpa0-1"; 239 samsung,pin-con-pdn = <0>; 240 samsung,pin-pud-pdn = <0>; 241 }; 242 243 // ... 244 }; 245 }; 246 247 - | 248 #include <dt-bindings/interrupt-controller/arm-gic.h> 249 250 pinctrl@11000000 { 251 compatible = "samsung,exynos4210-pinctrl"; 252 reg = <0x11000000 0x1000>; 253 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 254 255 wakeup-interrupt-controller { 256 compatible = "samsung,exynos4210-wakeup-eint"; 257 interrupt-parent = <&gic>; 258 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 259 }; 260 261 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 262 gpj0-gpio-bank { 263 gpio-controller; 264 #gpio-cells = <2>; 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 }; 268 269 /* Pin bank without external interrupts */ 270 gpy0-gpio-bank { 271 gpio-controller; 272 #gpio-cells = <2>; 273 }; 274 275 /* Pin bank with external direct wake-up interrupts */ 276 gpx0-gpio-bank { 277 gpio-controller; 278 #gpio-cells = <2>; 279 280 interrupt-controller; 281 interrupt-parent = <&gic>; 282 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 290 #interrupt-cells = <2>; 291 }; 292 293 // ... 294 295 sd0-clk-pins { 296 samsung,pins = "gpk0-0"; 297 samsung,pin-function = <2>; 298 samsung,pin-pud = <0>; 299 samsung,pin-drv = <3>; 300 }; 301 302 sd4-bus-width8-pins { 303 part-1-pins { 304 samsung,pins = "gpk0-3", "gpk0-4", 305 "gpk0-5", "gpk0-6"; 306 samsung,pin-function = <3>; 307 samsung,pin-pud = <3>; 308 samsung,pin-drv = <3>; 309 }; 310 311 part-2-pins { 312 samsung,pins = "gpk1-3", "gpk1-4", 313 "gpk1-5", "gpk1-6"; 314 samsung,pin-function = <4>; 315 samsung,pin-pud = <3>; 316 samsung,pin-drv = <3>; 317 }; 318 }; 319 320 // ... 321 322 otg-gp-pins { 323 samsung,pins = "gpx3-3"; 324 samsung,pin-function = <1>; 325 samsung,pin-pud = <0>; 326 samsung,pin-drv = <0>; 327 samsung,pin-val = <0>; 328 }; 329 }; 330 331 - | 332 #include <dt-bindings/interrupt-controller/arm-gic.h> 333 334 pinctrl@10580000 { 335 compatible = "samsung,exynos5433-pinctrl"; 336 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 337 338 pinctrl-names = "default"; 339 pinctrl-0 = <&initial_alive>; 340 341 wakeup-interrupt-controller { 342 compatible = "samsung,exynos5433-wakeup-eint", 343 "samsung,exynos7-wakeup-eint"; 344 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 345 }; 346 347 /* Pin bank with external direct wake-up interrupts */ 348 gpa0-gpio-bank { 349 gpio-controller; 350 #gpio-cells = <2>; 351 352 interrupt-controller; 353 interrupt-parent = <&gic>; 354 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 362 #interrupt-cells = <2>; 363 }; 364 365 // ... 366 367 te-irq-pins { 368 samsung,pins = "gpf1-3"; 369 samsung,pin-function = <0xf>; 370 }; 371 372 // .. 373 374 initial_alive: initial-state { 375 gpa0-0-pin { 376 samsung,pins = "gpa0-0"; 377 samsung,pin-function = <0>; 378 samsung,pin-pud = <1>; 379 samsung,pin-drv = <0>; 380 }; 381 382 // ... 383 }; 384 }; 385 386 - | 387 #include <dt-bindings/interrupt-controller/arm-gic.h> 388 389 pinctrl@114b0000 { 390 compatible = "samsung,exynos5433-pinctrl"; 391 reg = <0x114b0000 0x1000>; 392 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 393 power-domains = <&pd_aud>; 394 395 /* Pin bank with external GPIO or muxed external wake-up interrupts */ 396 gpz0-gpio-bank { 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 }; 402 403 // ... 404 405 i2s0-bus-pins { 406 samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", 407 "gpz0-4", "gpz0-5", "gpz0-6"; 408 samsung,pin-function = <2>; 409 samsung,pin-pud = <0>; 410 samsung,pin-drv = <0>; 411 }; 412 413 // ... 414 }; 415