xref: /linux/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml (revision c17ccefb611fdb346eef9be6bfbd0bfd04afa204) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Pinmux Controller
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip Pinmux Controller enables the IC to share one PAD
14  to several functional blocks. The sharing is done by multiplexing
15  the PAD input/output signals. For each PAD there are several muxing
16  options with option 0 being used as a GPIO.
17
18  Please refer to pinctrl-bindings.txt in this directory for details of the
19  common pinctrl bindings used by client devices, including the meaning of the
20  phrase "pin configuration node".
21
22  The Rockchip pin configuration node is a node of a group of pins which can be
23  used for a specific device or function. This node represents both mux and
24  config of the pins in that group. The 'pins' selects the function mode
25  (also named pin mode) this pin can work on and the 'config' configures
26  various pad settings such as pull-up, etc.
27
28  The pins are grouped into up to 9 individual pin banks which need to be
29  defined as gpio sub-nodes of the pinmux controller.
30
31properties:
32  compatible:
33    enum:
34      - rockchip,px30-pinctrl
35      - rockchip,rk2928-pinctrl
36      - rockchip,rk3036-pinctrl
37      - rockchip,rk3066a-pinctrl
38      - rockchip,rk3066b-pinctrl
39      - rockchip,rk3128-pinctrl
40      - rockchip,rk3188-pinctrl
41      - rockchip,rk3228-pinctrl
42      - rockchip,rk3288-pinctrl
43      - rockchip,rk3308-pinctrl
44      - rockchip,rk3328-pinctrl
45      - rockchip,rk3368-pinctrl
46      - rockchip,rk3399-pinctrl
47      - rockchip,rk3528-pinctrl
48      - rockchip,rk3562-pinctrl
49      - rockchip,rk3568-pinctrl
50      - rockchip,rk3576-pinctrl
51      - rockchip,rk3588-pinctrl
52      - rockchip,rv1108-pinctrl
53      - rockchip,rv1126-pinctrl
54
55  rockchip,grf:
56    $ref: /schemas/types.yaml#/definitions/phandle
57    description:
58      The phandle of the syscon node for the GRF registers.
59
60  rockchip,pmu:
61    $ref: /schemas/types.yaml#/definitions/phandle
62    description:
63      The phandle of the syscon node for the PMU registers,
64      as some SoCs carry parts of the iomux controller registers there.
65      Required for at least rk3188 and rk3288. On the rk3368 this should
66      point to the PMUGRF syscon.
67
68  "#address-cells":
69    enum: [1, 2]
70
71  "#size-cells":
72    enum: [1, 2]
73
74  ranges: true
75
76allOf:
77  - $ref: pinctrl.yaml#
78
79required:
80  - compatible
81  - rockchip,grf
82
83patternProperties:
84  "gpio@[0-9a-f]+$":
85    type: object
86
87    $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
88    deprecated: true
89
90    unevaluatedProperties: false
91
92  "pcfg-[a-z0-9-]+$":
93    type: object
94    properties:
95      bias-disable: true
96
97      bias-pull-down: true
98
99      bias-pull-pin-default: true
100
101      bias-pull-up: true
102
103      drive-strength:
104        minimum: 0
105        maximum: 20
106
107      input-enable: true
108
109      input-schmitt-enable: true
110
111      output-high: true
112
113      output-low: true
114
115    additionalProperties: false
116
117additionalProperties:
118  type: object
119  additionalProperties:
120    type: object
121    additionalProperties: false
122
123    properties:
124      rockchip,pins:
125        $ref: /schemas/types.yaml#/definitions/uint32-matrix
126        minItems: 1
127        items:
128          items:
129            - minimum: 0
130              maximum: 8
131              description:
132                Pin bank.
133            - minimum: 0
134              maximum: 31
135              description:
136                Pin bank index.
137            - minimum: 0
138              maximum: 14
139              description:
140                Mux 0 means GPIO and mux 1 to N means
141                the specific device function.
142            - description:
143                The phandle of a node contains the generic pinconfig options
144                to use as described in pinctrl-bindings.txt.
145
146examples:
147  - |
148    #include <dt-bindings/interrupt-controller/arm-gic.h>
149    #include <dt-bindings/pinctrl/rockchip.h>
150
151    pinctrl: pinctrl {
152      compatible = "rockchip,rk3066a-pinctrl";
153      rockchip,grf = <&grf>;
154
155      #address-cells = <1>;
156      #size-cells = <1>;
157      ranges;
158
159      gpio0: gpio@20034000 {
160        compatible = "rockchip,gpio-bank";
161        reg = <0x20034000 0x100>;
162        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
163        clocks = <&clk_gates8 9>;
164
165        gpio-controller;
166        #gpio-cells = <2>;
167
168        interrupt-controller;
169        #interrupt-cells = <2>;
170      };
171
172      pcfg_pull_default: pcfg-pull-default {
173        bias-pull-pin-default;
174      };
175
176      uart2 {
177        uart2_xfer: uart2-xfer {
178          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
179                          <1 RK_PB1 1 &pcfg_pull_default>;
180        };
181      };
182    };
183
184    uart2: serial@20064000 {
185      compatible = "snps,dw-apb-uart";
186      reg = <0x20064000 0x400>;
187      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
188      clocks = <&mux_uart2>;
189      pinctrl-0 = <&uart2_xfer>;
190      pinctrl-names = "default";
191      reg-io-width = <1>;
192      reg-shift = <2>;
193    };
194