xref: /linux/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Pinmux Controller
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip Pinmux Controller enables the IC to share one PAD
14  to several functional blocks. The sharing is done by multiplexing
15  the PAD input/output signals. For each PAD there are several muxing
16  options with option 0 being used as a GPIO.
17
18  Please refer to pinctrl-bindings.txt in this directory for details of the
19  common pinctrl bindings used by client devices, including the meaning of the
20  phrase "pin configuration node".
21
22  The Rockchip pin configuration node is a node of a group of pins which can be
23  used for a specific device or function. This node represents both mux and
24  config of the pins in that group. The 'pins' selects the function mode
25  (also named pin mode) this pin can work on and the 'config' configures
26  various pad settings such as pull-up, etc.
27
28  The pins are grouped into up to 9 individual pin banks which need to be
29  defined as gpio sub-nodes of the pinmux controller.
30
31properties:
32  compatible:
33    enum:
34      - rockchip,px30-pinctrl
35      - rockchip,rk2928-pinctrl
36      - rockchip,rk3036-pinctrl
37      - rockchip,rk3066a-pinctrl
38      - rockchip,rk3066b-pinctrl
39      - rockchip,rk3128-pinctrl
40      - rockchip,rk3188-pinctrl
41      - rockchip,rk3228-pinctrl
42      - rockchip,rk3288-pinctrl
43      - rockchip,rk3308-pinctrl
44      - rockchip,rk3328-pinctrl
45      - rockchip,rk3368-pinctrl
46      - rockchip,rk3399-pinctrl
47      - rockchip,rk3568-pinctrl
48      - rockchip,rk3588-pinctrl
49      - rockchip,rv1108-pinctrl
50      - rockchip,rv1126-pinctrl
51
52  rockchip,grf:
53    $ref: /schemas/types.yaml#/definitions/phandle
54    description:
55      The phandle of the syscon node for the GRF registers.
56
57  rockchip,pmu:
58    $ref: /schemas/types.yaml#/definitions/phandle
59    description:
60      The phandle of the syscon node for the PMU registers,
61      as some SoCs carry parts of the iomux controller registers there.
62      Required for at least rk3188 and rk3288. On the rk3368 this should
63      point to the PMUGRF syscon.
64
65  "#address-cells":
66    enum: [1, 2]
67
68  "#size-cells":
69    enum: [1, 2]
70
71  ranges: true
72
73allOf:
74  - $ref: pinctrl.yaml#
75
76required:
77  - compatible
78  - rockchip,grf
79
80patternProperties:
81  "gpio@[0-9a-f]+$":
82    type: object
83
84    $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
85    deprecated: true
86
87    unevaluatedProperties: false
88
89  "pcfg-[a-z0-9-]+$":
90    type: object
91    properties:
92      bias-disable: true
93
94      bias-pull-down: true
95
96      bias-pull-pin-default: true
97
98      bias-pull-up: true
99
100      drive-strength:
101        minimum: 0
102        maximum: 20
103
104      input-enable: true
105
106      input-schmitt-enable: true
107
108      output-high: true
109
110      output-low: true
111
112    additionalProperties: false
113
114additionalProperties:
115  type: object
116  additionalProperties:
117    type: object
118    additionalProperties: false
119
120    properties:
121      rockchip,pins:
122        $ref: /schemas/types.yaml#/definitions/uint32-matrix
123        minItems: 1
124        items:
125          items:
126            - minimum: 0
127              maximum: 8
128              description:
129                Pin bank.
130            - minimum: 0
131              maximum: 31
132              description:
133                Pin bank index.
134            - minimum: 0
135              maximum: 13
136              description:
137                Mux 0 means GPIO and mux 1 to N means
138                the specific device function.
139            - description:
140                The phandle of a node contains the generic pinconfig options
141                to use as described in pinctrl-bindings.txt.
142
143examples:
144  - |
145    #include <dt-bindings/interrupt-controller/arm-gic.h>
146    #include <dt-bindings/pinctrl/rockchip.h>
147
148    pinctrl: pinctrl {
149      compatible = "rockchip,rk3066a-pinctrl";
150      rockchip,grf = <&grf>;
151
152      #address-cells = <1>;
153      #size-cells = <1>;
154      ranges;
155
156      gpio0: gpio@20034000 {
157        compatible = "rockchip,gpio-bank";
158        reg = <0x20034000 0x100>;
159        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
160        clocks = <&clk_gates8 9>;
161
162        gpio-controller;
163        #gpio-cells = <2>;
164
165        interrupt-controller;
166        #interrupt-cells = <2>;
167      };
168
169      pcfg_pull_default: pcfg-pull-default {
170        bias-pull-pin-default;
171      };
172
173      uart2 {
174        uart2_xfer: uart2-xfer {
175          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
176                          <1 RK_PB1 1 &pcfg_pull_default>;
177        };
178      };
179    };
180
181    uart2: serial@20064000 {
182      compatible = "snps,dw-apb-uart";
183      reg = <0x20064000 0x400>;
184      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
185      clocks = <&mux_uart2>;
186      pinctrl-0 = <&uart2_xfer>;
187      pinctrl-names = "default";
188      reg-io-width = <1>;
189      reg-shift = <2>;
190    };
191