xref: /linux/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Pinmux Controller
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip Pinmux Controller enables the IC to share one PAD
14  to several functional blocks. The sharing is done by multiplexing
15  the PAD input/output signals. For each PAD there are several muxing
16  options with option 0 being used as a GPIO.
17
18  Please refer to pinctrl-bindings.txt in this directory for details of the
19  common pinctrl bindings used by client devices, including the meaning of the
20  phrase "pin configuration node".
21
22  The Rockchip pin configuration node is a node of a group of pins which can be
23  used for a specific device or function. This node represents both mux and
24  config of the pins in that group. The 'pins' selects the function mode
25  (also named pin mode) this pin can work on and the 'config' configures
26  various pad settings such as pull-up, etc.
27
28  The pins are grouped into up to 9 individual pin banks which need to be
29  defined as gpio sub-nodes of the pinmux controller.
30
31properties:
32  compatible:
33    enum:
34      - rockchip,px30-pinctrl
35      - rockchip,rk2928-pinctrl
36      - rockchip,rk3036-pinctrl
37      - rockchip,rk3066a-pinctrl
38      - rockchip,rk3066b-pinctrl
39      - rockchip,rk3128-pinctrl
40      - rockchip,rk3188-pinctrl
41      - rockchip,rk3228-pinctrl
42      - rockchip,rk3288-pinctrl
43      - rockchip,rk3308-pinctrl
44      - rockchip,rk3328-pinctrl
45      - rockchip,rk3368-pinctrl
46      - rockchip,rk3399-pinctrl
47      - rockchip,rk3506-pinctrl
48      - rockchip,rk3528-pinctrl
49      - rockchip,rk3562-pinctrl
50      - rockchip,rk3568-pinctrl
51      - rockchip,rk3576-pinctrl
52      - rockchip,rk3588-pinctrl
53      - rockchip,rv1103b-pinctrl
54      - rockchip,rv1108-pinctrl
55      - rockchip,rv1126-pinctrl
56
57  rockchip,grf:
58    $ref: /schemas/types.yaml#/definitions/phandle
59    description:
60      The phandle of the syscon node for the GRF registers.
61
62  rockchip,pmu:
63    $ref: /schemas/types.yaml#/definitions/phandle
64    description:
65      The phandle of the syscon node for the PMU registers,
66      as some SoCs carry parts of the iomux controller registers there.
67      Required for at least rk3188 and rk3288. On the rk3368 this should
68      point to the PMUGRF syscon.
69
70  "#address-cells":
71    enum: [1, 2]
72
73  "#size-cells":
74    enum: [1, 2]
75
76  ranges: true
77
78allOf:
79  - $ref: pinctrl.yaml#
80
81required:
82  - compatible
83  - rockchip,grf
84
85patternProperties:
86  "gpio@[0-9a-f]+$":
87    type: object
88
89    $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
90    deprecated: true
91
92    unevaluatedProperties: false
93
94  "pcfg-[a-z0-9-]+$":
95    type: object
96    properties:
97      bias-disable: true
98
99      bias-pull-down: true
100
101      bias-pull-pin-default: true
102
103      bias-pull-up: true
104
105      drive-strength:
106        minimum: 0
107        maximum: 20
108
109      input-enable: true
110
111      input-schmitt-enable: true
112
113      output-high: true
114
115      output-low: true
116
117    additionalProperties: false
118
119additionalProperties:
120  type: object
121  additionalProperties:
122    type: object
123    additionalProperties: false
124
125    properties:
126      rockchip,pins:
127        $ref: /schemas/types.yaml#/definitions/uint32-matrix
128        minItems: 1
129        items:
130          items:
131            - minimum: 0
132              maximum: 8
133              description:
134                Pin bank.
135            - minimum: 0
136              maximum: 31
137              description:
138                Pin bank index.
139            - minimum: 0
140              maximum: 14
141              description:
142                Mux 0 means GPIO and mux 1 to N means
143                the specific device function.
144            - description:
145                The phandle of a node contains the generic pinconfig options
146                to use as described in pinctrl-bindings.txt.
147
148examples:
149  - |
150    #include <dt-bindings/interrupt-controller/arm-gic.h>
151    #include <dt-bindings/pinctrl/rockchip.h>
152
153    pinctrl: pinctrl {
154      compatible = "rockchip,rk3066a-pinctrl";
155      rockchip,grf = <&grf>;
156
157      #address-cells = <1>;
158      #size-cells = <1>;
159      ranges;
160
161      gpio0: gpio@20034000 {
162        compatible = "rockchip,gpio-bank";
163        reg = <0x20034000 0x100>;
164        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
165        clocks = <&clk_gates8 9>;
166
167        gpio-controller;
168        #gpio-cells = <2>;
169
170        interrupt-controller;
171        #interrupt-cells = <2>;
172      };
173
174      pcfg_pull_default: pcfg-pull-default {
175        bias-pull-pin-default;
176      };
177
178      uart2 {
179        uart2_xfer: uart2-xfer {
180          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
181                          <1 RK_PB1 1 &pcfg_pull_default>;
182        };
183      };
184    };
185
186    uart2: serial@20064000 {
187      compatible = "snps,dw-apb-uart";
188      reg = <0x20064000 0x400>;
189      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
190      clocks = <&mux_uart2>;
191      pinctrl-0 = <&uart2_xfer>;
192      pinctrl-names = "default";
193      reg-io-width = <1>;
194      reg-shift = <2>;
195    };
196