xref: /linux/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Pinmux Controller
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip Pinmux Controller enables the IC to share one PAD
14  to several functional blocks. The sharing is done by multiplexing
15  the PAD input/output signals. For each PAD there are several muxing
16  options with option 0 being used as a GPIO.
17
18  Please refer to pinctrl-bindings.txt in this directory for details of the
19  common pinctrl bindings used by client devices, including the meaning of the
20  phrase "pin configuration node".
21
22  The Rockchip pin configuration node is a node of a group of pins which can be
23  used for a specific device or function. This node represents both mux and
24  config of the pins in that group. The 'pins' selects the function mode
25  (also named pin mode) this pin can work on and the 'config' configures
26  various pad settings such as pull-up, etc.
27
28  The pins are grouped into up to 9 individual pin banks which need to be
29  defined as gpio sub-nodes of the pinmux controller.
30
31properties:
32  compatible:
33    enum:
34      - rockchip,px30-pinctrl
35      - rockchip,rk2928-pinctrl
36      - rockchip,rk3036-pinctrl
37      - rockchip,rk3066a-pinctrl
38      - rockchip,rk3066b-pinctrl
39      - rockchip,rk3128-pinctrl
40      - rockchip,rk3188-pinctrl
41      - rockchip,rk3228-pinctrl
42      - rockchip,rk3288-pinctrl
43      - rockchip,rk3308-pinctrl
44      - rockchip,rk3328-pinctrl
45      - rockchip,rk3368-pinctrl
46      - rockchip,rk3399-pinctrl
47      - rockchip,rk3506-pinctrl
48      - rockchip,rk3528-pinctrl
49      - rockchip,rk3562-pinctrl
50      - rockchip,rk3568-pinctrl
51      - rockchip,rk3576-pinctrl
52      - rockchip,rk3588-pinctrl
53      - rockchip,rv1103b-pinctrl
54      - rockchip,rv1106-pinctrl
55      - rockchip,rv1108-pinctrl
56      - rockchip,rv1126-pinctrl
57
58  rockchip,grf:
59    $ref: /schemas/types.yaml#/definitions/phandle
60    description:
61      The phandle of the syscon node for the GRF registers.
62
63  rockchip,pmu:
64    $ref: /schemas/types.yaml#/definitions/phandle
65    description:
66      The phandle of the syscon node for the PMU registers,
67      as some SoCs carry parts of the iomux controller registers there.
68      Required for at least rk3188 and rk3288. On the rk3368 this should
69      point to the PMUGRF syscon.
70
71  "#address-cells":
72    enum: [1, 2]
73
74  "#size-cells":
75    enum: [1, 2]
76
77  ranges: true
78
79allOf:
80  - $ref: pinctrl.yaml#
81
82required:
83  - compatible
84  - rockchip,grf
85
86patternProperties:
87  "gpio@[0-9a-f]+$":
88    type: object
89
90    $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
91    deprecated: true
92
93    unevaluatedProperties: false
94
95  "pcfg-[a-z0-9-]+$":
96    type: object
97    properties:
98      bias-disable: true
99
100      bias-pull-down: true
101
102      bias-pull-pin-default: true
103
104      bias-pull-up: true
105
106      drive-strength:
107        minimum: 0
108        maximum: 20
109
110      input-enable: true
111
112      input-schmitt-enable: true
113
114      output-high: true
115
116      output-low: true
117
118    additionalProperties: false
119
120additionalProperties:
121  type: object
122  additionalProperties:
123    type: object
124    additionalProperties: false
125
126    properties:
127      rockchip,pins:
128        $ref: /schemas/types.yaml#/definitions/uint32-matrix
129        minItems: 1
130        items:
131          items:
132            - minimum: 0
133              maximum: 8
134              description:
135                Pin bank.
136            - minimum: 0
137              maximum: 31
138              description:
139                Pin bank index.
140            - minimum: 0
141              maximum: 14
142              description:
143                Mux 0 means GPIO and mux 1 to N means
144                the specific device function.
145            - description:
146                The phandle of a node contains the generic pinconfig options
147                to use as described in pinctrl-bindings.txt.
148
149examples:
150  - |
151    #include <dt-bindings/interrupt-controller/arm-gic.h>
152    #include <dt-bindings/pinctrl/rockchip.h>
153
154    pinctrl: pinctrl {
155      compatible = "rockchip,rk3066a-pinctrl";
156      rockchip,grf = <&grf>;
157
158      #address-cells = <1>;
159      #size-cells = <1>;
160      ranges;
161
162      gpio0: gpio@20034000 {
163        compatible = "rockchip,gpio-bank";
164        reg = <0x20034000 0x100>;
165        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
166        clocks = <&clk_gates8 9>;
167
168        gpio-controller;
169        #gpio-cells = <2>;
170
171        interrupt-controller;
172        #interrupt-cells = <2>;
173      };
174
175      pcfg_pull_default: pcfg-pull-default {
176        bias-pull-pin-default;
177      };
178
179      uart2 {
180        uart2_xfer: uart2-xfer {
181          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
182                          <1 RK_PB1 1 &pcfg_pull_default>;
183        };
184      };
185    };
186
187    uart2: serial@20064000 {
188      compatible = "snps,dw-apb-uart";
189      reg = <0x20064000 0x400>;
190      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
191      clocks = <&mux_uart2>;
192      pinctrl-0 = <&uart2_xfer>;
193      pinctrl-names = "default";
194      reg-io-width = <1>;
195      reg-shift = <2>;
196    };
197