xref: /linux/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml (revision 1027cd8084bbcdf80d8a096d5e2c6da91402fc3c) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Pinmux Controller
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip Pinmux Controller enables the IC to share one PAD
14  to several functional blocks. The sharing is done by multiplexing
15  the PAD input/output signals. For each PAD there are several muxing
16  options with option 0 being used as a GPIO.
17
18  Please refer to pinctrl-bindings.txt in this directory for details of the
19  common pinctrl bindings used by client devices, including the meaning of the
20  phrase "pin configuration node".
21
22  The Rockchip pin configuration node is a node of a group of pins which can be
23  used for a specific device or function. This node represents both mux and
24  config of the pins in that group. The 'pins' selects the function mode
25  (also named pin mode) this pin can work on and the 'config' configures
26  various pad settings such as pull-up, etc.
27
28  The pins are grouped into up to 9 individual pin banks which need to be
29  defined as gpio sub-nodes of the pinmux controller.
30
31properties:
32  compatible:
33    enum:
34      - rockchip,px30-pinctrl
35      - rockchip,rk2928-pinctrl
36      - rockchip,rk3036-pinctrl
37      - rockchip,rk3066a-pinctrl
38      - rockchip,rk3066b-pinctrl
39      - rockchip,rk3128-pinctrl
40      - rockchip,rk3188-pinctrl
41      - rockchip,rk3228-pinctrl
42      - rockchip,rk3288-pinctrl
43      - rockchip,rk3308-pinctrl
44      - rockchip,rk3328-pinctrl
45      - rockchip,rk3368-pinctrl
46      - rockchip,rk3399-pinctrl
47      - rockchip,rk3562-pinctrl
48      - rockchip,rk3568-pinctrl
49      - rockchip,rk3576-pinctrl
50      - rockchip,rk3588-pinctrl
51      - rockchip,rv1108-pinctrl
52      - rockchip,rv1126-pinctrl
53
54  rockchip,grf:
55    $ref: /schemas/types.yaml#/definitions/phandle
56    description:
57      The phandle of the syscon node for the GRF registers.
58
59  rockchip,pmu:
60    $ref: /schemas/types.yaml#/definitions/phandle
61    description:
62      The phandle of the syscon node for the PMU registers,
63      as some SoCs carry parts of the iomux controller registers there.
64      Required for at least rk3188 and rk3288. On the rk3368 this should
65      point to the PMUGRF syscon.
66
67  "#address-cells":
68    enum: [1, 2]
69
70  "#size-cells":
71    enum: [1, 2]
72
73  ranges: true
74
75allOf:
76  - $ref: pinctrl.yaml#
77
78required:
79  - compatible
80  - rockchip,grf
81
82patternProperties:
83  "gpio@[0-9a-f]+$":
84    type: object
85
86    $ref: /schemas/gpio/rockchip,gpio-bank.yaml#
87    deprecated: true
88
89    unevaluatedProperties: false
90
91  "pcfg-[a-z0-9-]+$":
92    type: object
93    properties:
94      bias-disable: true
95
96      bias-pull-down: true
97
98      bias-pull-pin-default: true
99
100      bias-pull-up: true
101
102      drive-strength:
103        minimum: 0
104        maximum: 20
105
106      input-enable: true
107
108      input-schmitt-enable: true
109
110      output-high: true
111
112      output-low: true
113
114    additionalProperties: false
115
116additionalProperties:
117  type: object
118  additionalProperties:
119    type: object
120    additionalProperties: false
121
122    properties:
123      rockchip,pins:
124        $ref: /schemas/types.yaml#/definitions/uint32-matrix
125        minItems: 1
126        items:
127          items:
128            - minimum: 0
129              maximum: 8
130              description:
131                Pin bank.
132            - minimum: 0
133              maximum: 31
134              description:
135                Pin bank index.
136            - minimum: 0
137              maximum: 13
138              description:
139                Mux 0 means GPIO and mux 1 to N means
140                the specific device function.
141            - description:
142                The phandle of a node contains the generic pinconfig options
143                to use as described in pinctrl-bindings.txt.
144
145examples:
146  - |
147    #include <dt-bindings/interrupt-controller/arm-gic.h>
148    #include <dt-bindings/pinctrl/rockchip.h>
149
150    pinctrl: pinctrl {
151      compatible = "rockchip,rk3066a-pinctrl";
152      rockchip,grf = <&grf>;
153
154      #address-cells = <1>;
155      #size-cells = <1>;
156      ranges;
157
158      gpio0: gpio@20034000 {
159        compatible = "rockchip,gpio-bank";
160        reg = <0x20034000 0x100>;
161        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
162        clocks = <&clk_gates8 9>;
163
164        gpio-controller;
165        #gpio-cells = <2>;
166
167        interrupt-controller;
168        #interrupt-cells = <2>;
169      };
170
171      pcfg_pull_default: pcfg-pull-default {
172        bias-pull-pin-default;
173      };
174
175      uart2 {
176        uart2_xfer: uart2-xfer {
177          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
178                          <1 RK_PB1 1 &pcfg_pull_default>;
179        };
180      };
181    };
182
183    uart2: serial@20064000 {
184      compatible = "snps,dw-apb-uart";
185      reg = <0x20064000 0x400>;
186      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
187      clocks = <&mux_uart2>;
188      pinctrl-0 = <&uart2_xfer>;
189      pinctrl-names = "default";
190      reg-io-width = <1>;
191      reg-shift = <2>;
192    };
193