1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12 13description: 14 The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and 15 GPIO controller. 16 Pin multiplexing and GPIO configuration is performed on a per-pin basis. 17 Each port features up to 8 pins, each of them configurable for GPIO function 18 (port mode) or in alternate function mode. 19 Up to 8 different alternate function modes exist for each single pin. 20 21properties: 22 compatible: 23 oneOf: 24 - items: 25 - enum: 26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five 27 - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} 28 - renesas,r9a08g045-pinctrl # RZ/G3S 29 - renesas,r9a09g057-pinctrl # RZ/V2H(P) 30 31 - items: 32 - enum: 33 - renesas,r9a07g054-pinctrl # RZ/V2L 34 - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L 35 36 reg: 37 maxItems: 1 38 39 gpio-controller: true 40 41 '#gpio-cells': 42 const: 2 43 description: 44 The first cell contains the global GPIO port index, constructed using the 45 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the 46 second cell represents consumer flag as mentioned in ../gpio/gpio.txt 47 E.g. "RZG2L_GPIO(39, 1)" for P39_1. 48 49 gpio-ranges: 50 maxItems: 1 51 52 interrupt-controller: true 53 54 '#interrupt-cells': 55 const: 2 56 description: 57 The first cell contains the global GPIO port index, constructed using the 58 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the 59 second cell is used to specify the flag. 60 E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is 61 being used as an interrupt. 62 63 clocks: 64 maxItems: 1 65 66 power-domains: 67 maxItems: 1 68 69 resets: 70 oneOf: 71 - items: 72 - description: GPIO_RSTN signal 73 - description: GPIO_PORT_RESETN signal 74 - description: GPIO_SPARE_RESETN signal 75 - items: 76 - description: PFC main reset 77 - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins 78 79additionalProperties: 80 anyOf: 81 - type: object 82 additionalProperties: false 83 allOf: 84 - $ref: pincfg-node.yaml# 85 - $ref: pinmux-node.yaml# 86 87 description: 88 Pin controller client devices use pin configuration subnodes (children 89 and grandchildren) for desired pin configuration. 90 Client device subnodes use below standard properties. 91 92 properties: 93 pinmux: 94 description: 95 Values are constructed from GPIO port number, pin number, and 96 alternate function configuration number using the RZG2L_PORT_PINMUX() 97 helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>. 98 pins: true 99 drive-strength: 100 enum: [ 2, 4, 8, 12 ] 101 drive-strength-microamp: 102 enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700, 103 5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000, 104 10000 ] 105 output-impedance-ohms: 106 enum: [ 33, 50, 66, 100 ] 107 power-source: 108 description: I/O voltage in millivolt. 109 enum: [ 1800, 2500, 3300 ] 110 slew-rate: true 111 gpio-hog: true 112 gpios: true 113 input: true 114 input-enable: true 115 output-enable: true 116 output-high: true 117 output-low: true 118 line-name: true 119 bias-disable: true 120 bias-pull-down: true 121 bias-pull-up: true 122 input-schmitt-enable: true 123 input-schmitt-disable: true 124 drive-open-drain: true 125 drive-push-pull: true 126 renesas,output-impedance: 127 description: 128 Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this 129 property corresponds to register bit values that can be set in the PFC_IOLH_mn 130 register, which adjusts the drive strength value and is pin-dependent. 131 $ref: /schemas/types.yaml#/definitions/uint32 132 enum: [0, 1, 2, 3] 133 134 - type: object 135 additionalProperties: 136 $ref: "#/additionalProperties/anyOf/0" 137 138allOf: 139 - $ref: pinctrl.yaml# 140 141 - if: 142 properties: 143 compatible: 144 contains: 145 const: renesas,r9a09g057-pinctrl 146 then: 147 properties: 148 resets: 149 maxItems: 2 150 else: 151 properties: 152 resets: 153 minItems: 3 154 155required: 156 - compatible 157 - reg 158 - gpio-controller 159 - '#gpio-cells' 160 - gpio-ranges 161 - interrupt-controller 162 - '#interrupt-cells' 163 - clocks 164 - power-domains 165 - resets 166 167examples: 168 - | 169 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 170 #include <dt-bindings/clock/r9a07g044-cpg.h> 171 172 pinctrl: pinctrl@11030000 { 173 compatible = "renesas,r9a07g044-pinctrl"; 174 reg = <0x11030000 0x10000>; 175 176 gpio-controller; 177 #gpio-cells = <2>; 178 gpio-ranges = <&pinctrl 0 0 392>; 179 interrupt-controller; 180 #interrupt-cells = <2>; 181 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; 182 resets = <&cpg R9A07G044_GPIO_RSTN>, 183 <&cpg R9A07G044_GPIO_PORT_RESETN>, 184 <&cpg R9A07G044_GPIO_SPARE_RESETN>; 185 power-domains = <&cpg>; 186 187 scif0_pins: serial0 { 188 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */ 189 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */ 190 }; 191 192 i2c1_pins: i2c1 { 193 pins = "RIIC1_SDA", "RIIC1_SCL"; 194 input-enable; 195 }; 196 197 sd1-pwr-en-hog { 198 gpio-hog; 199 gpios = <RZG2L_GPIO(39, 2) 0>; 200 output-high; 201 line-name = "sd1_pwr_en"; 202 }; 203 204 sdhi1_pins: sd1 { 205 sd1_mux { 206 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */ 207 <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */ 208 power-source = <3300>; 209 }; 210 211 sd1_data { 212 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; 213 power-source = <3300>; 214 }; 215 216 sd1_ctrl { 217 pins = "SD1_CLK", "SD1_CMD"; 218 power-source = <3300>; 219 }; 220 }; 221 }; 222