1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/A1 combined Pin and GPIO controller 8 9maintainers: 10 - Jacopo Mondi <jacopo+renesas@jmondi.org> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 12 13description: 14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO 15 controller, named "Ports" in the hardware reference manual. 16 Pin multiplexing and GPIO configuration is performed on a per-pin basis 17 writing configuration values to per-port register sets. 18 Each "port" features up to 16 pins, each of them configurable for GPIO 19 function (port mode) or in alternate function mode. 20 Up to 8 different alternate function modes exist for each single pin. 21 22properties: 23 compatible: 24 oneOf: 25 - const: renesas,r7s72100-ports # RZ/A1H 26 - items: 27 - const: renesas,r7s72101-ports # RZ/A1M 28 - const: renesas,r7s72100-ports # fallback 29 - const: renesas,r7s72102-ports # RZ/A1L 30 31 reg: 32 maxItems: 1 33 34allOf: 35 - $ref: "pinctrl.yaml#" 36 37required: 38 - compatible 39 - reg 40 41patternProperties: 42 "^gpio-[0-9]*$": 43 type: object 44 additionalProperties: false 45 46 description: 47 Each port of the r7s72100 pin controller hardware is itself a GPIO 48 controller. 49 Different SoCs have different numbers of available pins per port, but 50 generally speaking, each of them can be configured in GPIO ("port") mode 51 on this hardware. 52 Describe GPIO controllers using sub-nodes with the following properties. 53 54 properties: 55 gpio-controller: true 56 57 '#gpio-cells': 58 const: 2 59 60 gpio-ranges: 61 maxItems: 1 62 63 required: 64 - gpio-controller 65 - '#gpio-cells' 66 - gpio-ranges 67 68 69additionalProperties: 70 anyOf: 71 - type: object 72 allOf: 73 - $ref: pincfg-node.yaml# 74 - $ref: pinmux-node.yaml# 75 76 description: 77 A pin multiplexing sub-node describes how to configure a set of (or a 78 single) pin in some desired alternate function mode. 79 A single sub-node may define several pin configurations. 80 A few alternate function require special pin configuration flags to be 81 supplied along with the alternate function configuration number. 82 The hardware reference manual specifies when a pin function requires 83 "software IO driven" mode to be specified. To do so use the generic 84 properties from the <include/linux/pinctrl/pinconf_generic.h> header 85 file to instruct the pin controller to perform the desired pin 86 configuration operation. 87 The hardware reference manual specifies when a pin has to be configured 88 to work in bi-directional mode and when the IO direction has to be 89 specified by software. Bi-directional pins must be managed by the pin 90 controller driver internally, while software driven IO direction has to 91 be explicitly selected when multiple options are available. 92 93 properties: 94 pinmux: 95 description: | 96 Integer array representing pin number and pin multiplexing 97 configuration. 98 When a pin has to be configured in alternate function mode, use 99 this property to identify the pin by its global index, and provide 100 its alternate function configuration number along with it. 101 When multiple pins are required to be configured as part of the 102 same alternate function they shall be specified as members of the 103 same argument list of a single "pinmux" property. 104 Helper macros to ease assembling the pin index from its position 105 (port where it sits on and pin number) and alternate function 106 identifier are provided by the pin controller header file at: 107 <include/dt-bindings/pinctrl/r7s72100-pinctrl.h> 108 Integers values in "pinmux" argument list are assembled as: 109 ((PORT * 16 + PIN) | MUX_FUNC << 16) 110 111 phandle: true 112 input-enable: true 113 output-enable: true 114 115 required: 116 - pinmux 117 118 additionalProperties: false 119 120 - type: object 121 properties: 122 phandle: true 123 124 additionalProperties: 125 $ref: "#/additionalProperties/anyOf/0" 126 127examples: 128 - | 129 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 130 pinctrl: pinctrl@fcfe3000 { 131 compatible = "renesas,r7s72100-ports"; 132 133 reg = <0xfcfe3000 0x4230>; 134 135 /* 136 * A GPIO controller node, controlling 16 pins indexed from 0. 137 * The GPIO controller base in the global pin indexing space is pin 138 * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] 139 * in the global pin indexing space. 140 */ 141 port3: gpio-3 { 142 gpio-controller; 143 #gpio-cells = <2>; 144 gpio-ranges = <&pinctrl 0 48 16>; 145 }; 146 147 /* 148 * A serial communication interface with a TX output pin and an RX 149 * input pin. 150 * Pin #0 on port #3 is configured as alternate function #6. 151 * Pin #2 on port #3 is configured as alternate function #4. 152 */ 153 scif2_pins: serial2 { 154 pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; 155 }; 156 157 158 /* 159 * I2c master: both SDA and SCL pins need bi-directional operations 160 * Pin #4 on port #1 is configured as alternate function #1. 161 * Pin #5 on port #1 is configured as alternate function #1. 162 * Both need to work in bi-directional mode, the driver must manage 163 * this internally. 164 */ 165 i2c2_pins: i2c2 { 166 pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>; 167 }; 168 169 170 /* 171 * Multi-function timer input and output compare pins. 172 */ 173 tioc0_pins: tioc0 { 174 /* 175 * Configure TIOC0A as software driven input 176 * Pin #0 on port #4 is configured as alternate function #2 177 * with IO direction specified by software as input. 178 */ 179 tioc0_input_pins { 180 pinmux = <RZA1_PINMUX(4, 0, 2)>; 181 input-enable; 182 }; 183 184 /* 185 * Configure TIOC0B as software driven output 186 * Pin #1 on port #4 is configured as alternate function #1 187 * with IO direction specified by software as output. 188 */ 189 tioc0_output_pins { 190 pinmux = <RZA1_PINMUX(4, 1, 1)>; 191 output-enable; 192 }; 193 }; 194 }; 195