14d0e6267SGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 24d0e6267SGeert Uytterhoeven%YAML 1.2 34d0e6267SGeert Uytterhoeven--- 44d0e6267SGeert Uytterhoeven$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml# 54d0e6267SGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml# 64d0e6267SGeert Uytterhoeven 74d0e6267SGeert Uytterhoeventitle: Renesas RZ/A2 combined Pin and GPIO controller 84d0e6267SGeert Uytterhoeven 94d0e6267SGeert Uytterhoevenmaintainers: 104d0e6267SGeert Uytterhoeven - Chris Brandt <chris.brandt@renesas.com> 114d0e6267SGeert Uytterhoeven - Geert Uytterhoeven <geert+renesas@glider.be> 124d0e6267SGeert Uytterhoeven 134d0e6267SGeert Uytterhoevendescription: 144d0e6267SGeert Uytterhoeven The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO 154d0e6267SGeert Uytterhoeven controller. 164d0e6267SGeert Uytterhoeven Pin multiplexing and GPIO configuration is performed on a per-pin basis. 174d0e6267SGeert Uytterhoeven Each port features up to 8 pins, each of them configurable for GPIO function 184d0e6267SGeert Uytterhoeven (port mode) or in alternate function mode. 194d0e6267SGeert Uytterhoeven Up to 8 different alternate function modes exist for each single pin. 204d0e6267SGeert Uytterhoeven 214d0e6267SGeert Uytterhoevenproperties: 224d0e6267SGeert Uytterhoeven compatible: 234d0e6267SGeert Uytterhoeven const: "renesas,r7s9210-pinctrl" # RZ/A2M 244d0e6267SGeert Uytterhoeven 254d0e6267SGeert Uytterhoeven reg: 264d0e6267SGeert Uytterhoeven maxItems: 1 274d0e6267SGeert Uytterhoeven 284d0e6267SGeert Uytterhoeven gpio-controller: true 294d0e6267SGeert Uytterhoeven 304d0e6267SGeert Uytterhoeven '#gpio-cells': 314d0e6267SGeert Uytterhoeven const: 2 324d0e6267SGeert Uytterhoeven description: 334d0e6267SGeert Uytterhoeven The first cell contains the global GPIO port index, constructed using the 344d0e6267SGeert Uytterhoeven RZA2_PIN() helper macro in r7s9210-pinctrl.h. 354d0e6267SGeert Uytterhoeven E.g. "RZA2_PIN(PORT6, 0)" for P6_0. 364d0e6267SGeert Uytterhoeven 374d0e6267SGeert Uytterhoeven gpio-ranges: 384d0e6267SGeert Uytterhoeven maxItems: 1 394d0e6267SGeert Uytterhoeven 404d0e6267SGeert UytterhoevenpatternProperties: 414d0e6267SGeert Uytterhoeven "^.*$": 424d0e6267SGeert Uytterhoeven if: 434d0e6267SGeert Uytterhoeven type: object 444d0e6267SGeert Uytterhoeven then: 454d0e6267SGeert Uytterhoeven allOf: 464d0e6267SGeert Uytterhoeven - $ref: pincfg-node.yaml# 474d0e6267SGeert Uytterhoeven - $ref: pinmux-node.yaml# 484d0e6267SGeert Uytterhoeven description: 494d0e6267SGeert Uytterhoeven The child nodes of the pin controller designate pins to be used for 504d0e6267SGeert Uytterhoeven specific peripheral functions or as GPIO. 514d0e6267SGeert Uytterhoeven 524d0e6267SGeert Uytterhoeven A pin multiplexing sub-node describes how to configure a set of 534d0e6267SGeert Uytterhoeven (or a single) pin in some desired alternate function mode. 544d0e6267SGeert Uytterhoeven The values for the pinmux properties are a combination of port name, 554d0e6267SGeert Uytterhoeven pin number and the desired function index. Use the RZA2_PINMUX macro 564d0e6267SGeert Uytterhoeven located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily 574d0e6267SGeert Uytterhoeven define these. 584d0e6267SGeert Uytterhoeven For assigning GPIO pins, use the macro RZA2_PIN also in 594d0e6267SGeert Uytterhoeven to express the desired port pin. 604d0e6267SGeert Uytterhoeven 614d0e6267SGeert Uytterhoeven properties: 624d0e6267SGeert Uytterhoeven phandle: true 634d0e6267SGeert Uytterhoeven 644d0e6267SGeert Uytterhoeven pinmux: 654d0e6267SGeert Uytterhoeven description: 664d0e6267SGeert Uytterhoeven Values are constructed from GPIO port number, pin number, and 674d0e6267SGeert Uytterhoeven alternate function configuration number using the RZA2_PINMUX() 684d0e6267SGeert Uytterhoeven helper macro in r7s9210-pinctrl.h. 694d0e6267SGeert Uytterhoeven 704d0e6267SGeert Uytterhoeven required: 714d0e6267SGeert Uytterhoeven - pinmux 724d0e6267SGeert Uytterhoeven 734d0e6267SGeert Uytterhoeven additionalProperties: false 744d0e6267SGeert Uytterhoeven 75c09acbc4SRafał MiłeckiallOf: 76*49cd1dd1SRob Herring - $ref: pinctrl.yaml# 77c09acbc4SRafał Miłecki 784d0e6267SGeert Uytterhoevenrequired: 794d0e6267SGeert Uytterhoeven - compatible 804d0e6267SGeert Uytterhoeven - reg 814d0e6267SGeert Uytterhoeven - gpio-controller 824d0e6267SGeert Uytterhoeven - '#gpio-cells' 834d0e6267SGeert Uytterhoeven - gpio-ranges 844d0e6267SGeert Uytterhoeven 854d0e6267SGeert UytterhoevenadditionalProperties: false 864d0e6267SGeert Uytterhoeven 874d0e6267SGeert Uytterhoevenexamples: 884d0e6267SGeert Uytterhoeven - | 894d0e6267SGeert Uytterhoeven #include <dt-bindings/pinctrl/r7s9210-pinctrl.h> 90d4691b7fSGeert Uytterhoeven pinctrl: pinctrl@fcffe000 { 914d0e6267SGeert Uytterhoeven compatible = "renesas,r7s9210-pinctrl"; 924d0e6267SGeert Uytterhoeven reg = <0xfcffe000 0x1000>; 934d0e6267SGeert Uytterhoeven 944d0e6267SGeert Uytterhoeven gpio-controller; 954d0e6267SGeert Uytterhoeven #gpio-cells = <2>; 964d0e6267SGeert Uytterhoeven gpio-ranges = <&pinctrl 0 0 176>; 974d0e6267SGeert Uytterhoeven 984d0e6267SGeert Uytterhoeven /* Serial Console */ 994d0e6267SGeert Uytterhoeven scif4_pins: serial4 { 1004d0e6267SGeert Uytterhoeven pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */ 1014d0e6267SGeert Uytterhoeven <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */ 1024d0e6267SGeert Uytterhoeven }; 1034d0e6267SGeert Uytterhoeven }; 104